From: lkcl Date: Sun, 12 Jun 2022 04:32:26 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~1841 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2f8ef936b7d29379e11d739407393e8f4a425579;p=libreriscv.git --- diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn index 6793f9440..23c69a491 100644 --- a/openpower/sv/mv.swizzle.mdwn +++ b/openpower/sv/mv.swizzle.mdwn @@ -72,6 +72,10 @@ this gives a 12 bit immediate across bits 16 to 25 and 29-30. * 3 bits Z * 3 bits W +| 0.2 |3.5 |6.8|9.11| +|-----|----|---|----| +|X | Y | Z | W | + the options are: * 0b000 to indicate "skip". this is equivalent to predicate masking @@ -82,8 +86,9 @@ the options are: Evaluating efforts to encode 12 bit swizzle into less proved unsuccessful: 7^4 comes out to 2,400 which is larger than 11 bits. -Note that 7 options are needed (not 6) because the 7th option allows predicate masking to be encoded within the swizzle immediate. -For example this allows "W..Y" to be specified, "copy W to position X, +Note that 7 options are needed (not 6) because the 7th option allows static +predicate masking to be encoded within the swizzle immediate. +For example this allows "W..Y" to specify: "copy W to position X, and Y to position W, leave the other two positions Y and Z unaltered" # RM Mode Concept: