From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 21 Feb 2019 19:15:25 +0000 (-0800)
Subject: write_xaiger to use original bit for co, not sigmap()-ed bit
X-Git-Tag: working-ls180~1237^2~281
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2f96a0ed32799eba95837d0b64953b889e607c22;p=yosys.git

write_xaiger to use original bit for co, not sigmap()-ed bit
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 56d361fff..b0602dbd8 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -210,9 +210,12 @@ struct XAigerWriter
 					Wire *w = b.wire;
 					if (!w) continue;
 					if (cell->input(c.first)) {
-						SigBit I = sigmap(b);
-						if (!w->port_input)
-							co_bits.insert(I);
+						if (!w->port_input) {
+							SigBit I = sigmap(b);
+							if (I != b)
+								alias_map[b] = I;
+							co_bits.insert(b);
+						}
 					}
 					else if (cell->output(c.first)) {
 						SigBit O = sigmap(b);