From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 29 Jul 2022 01:17:33 +0000 (+0100)
Subject: reduce table size
X-Git-Tag: opf_rfc_ls005_v1~968
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2fae1ae08126c3eae06273a1000a98a43115b4b6;p=libreriscv.git

reduce table size
---

diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn
index b97698d68..4392ba53a 100644
--- a/openpower/sv/comparison_table.mdwn
+++ b/openpower/sv/comparison_table.mdwn
@@ -1,14 +1,14 @@
 **ISA Comparison Table** - discussion and research at <https://bugs.libre-soc.org/show_bug.cgi?id=893>
 
-|ISA <br>name  |Num <br>opcodes|Num <br>intrinsics|Taxonomy / <br> Class|setvl <br> scalable|Predicate <br> Masks|Twin <br> Predication|Explicit <br> Vector regs|128-bit <br> ops|Bigint  |LDST <br> Fault-First|Data-dependent <br> Fail-first|Predicate-<br> Result|Matrix HW<br> support|
-|--------------|---------------|------------------|---------------------|-------------------|--------------------|---------------------|-------------------------|----------------|--------|---------------------|------------------------------|---------------------|---------------------|
-|Draft SVP64   |5 (1)          |see (25)          |Scalable (2)         |yes                |yes                 |yes (3)              |no (4)                   |see (5)         |yes (6) |yes (7)              |yes (8)                       |yes (9)              |yes (10)             |
-|VSX           |700+           |700+? (26)        |Packed SIMD          |no                 |no                  |no                   |yes (11)                 |yes             |no      |no                   |no                            |no                   |yes (12)             |
-|NEON          |~250 (13)      |7088 (27)         |Packed SIMD          |no                 |no                  |no                   |yes                      |yes             |no      |no                   |no                            |no                   |no                   |
-|SVE2          |~1000 (14)     |6040 (28)         |Predicated SIMD(15)  |no (15)            |yes                 |no                   |yes                      |yes             |no      |yes (7)              |no                            |no                   |yes (32)             |
-|AVX512 (16)   |~1000s (17)    |7256 (29)         |Predicated SIMD      |no                 |yes                 |no                   |yes                      |yes             |no      |no                   |no                            |no                   |no                   |
-|RVV (18)      |~190 (19)      |~25000 (30)       |Scalable (20)        |yes                |yes                 |no                   |yes                      |yes (21)        |no      |yes                  |no                            |no                   |no                   |
-|Aurora SX(22) |~200 (23)      |unknown (31)      |Scalable (24)        |yes                |yes                 |no                   |yes                      |no              |no      |no                   |no                            |no                   |?                    |
+|ISA <br>name  |Num <br>opcodes|Num <br>intrinsics|Taxonomy / <br> Class|setvl <br> scalable|Predicate <br> Masks|Twin <br> Predication|Explicit <br> Vector regs|128-bit <br> ops|Bigint  |LDST <br> Fault-First|Data-dep<br> Fail-first|Pred-<br> Result|Matrix HW<br> support|
+|--------------|---------------|------------------|---------------------|-------------------|--------------------|---------------------|-------------------------|----------------|--------|---------------------|-----------------------|----------------|---------------------|
+|Draft SVP64   |5 (1)          |see (25)          |Scalable (2)         |yes                |yes                 |yes (3)              |no (4)                   |see (5)         |yes (6) |yes (7)              |yes (8)                |yes (9)         |yes (10)             |
+|VSX           |700+           |700+? (26)        |Packed SIMD          |no                 |no                  |no                   |yes (11)                 |yes             |no      |no                   |no                     |no              |yes (12)             |
+|NEON          |~250 (13)      |7088 (27)         |Packed SIMD          |no                 |no                  |no                   |yes                      |yes             |no      |no                   |no                     |no              |no                   |
+|SVE2          |~1000 (14)     |6040 (28)         |Predicated SIMD(15)  |no (15)            |yes                 |no                   |yes                      |yes             |no      |yes (7)              |no                     |no              |yes (32)             |
+|AVX512 (16)   |~1000s (17)    |7256 (29)         |Predicated SIMD      |no                 |yes                 |no                   |yes                      |yes             |no      |no                   |no                     |no              |no                   |
+|RVV (18)      |~190 (19)      |~25000 (30)       |Scalable (20)        |yes                |yes                 |no                   |yes                      |yes (21)        |no      |yes                  |no                     |no              |no                   |
+|Aurora SX(22) |~200 (23)      |unknown (31)      |Scalable (24)        |yes                |yes                 |no                   |yes                      |no              |no      |no                   |no                     |no              |?                    |
 
 * (1): plus EXT001 24-bit prefixing using 25% of EXT001 space. See [[sv/svp64]]
 * (2): A 2-Dimensional Scalable Vector ISA **specifically designed for the Power ISA** with both Horizontal-First and Vertical-First Modes. See [[sv/vector_isa_comparison]]