From: Jacob Lifshay Date: Thu, 29 Sep 2022 03:02:58 +0000 (-0700) Subject: rename divrem2du->divmod2du for consistency with PowerISA mod* instructions X-Git-Tag: opf_rfc_ls005_v1~272 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2fbac071499ad33d5bfc91d07d768df84b5ec84d;p=libreriscv.git rename divrem2du->divmod2du for consistency with PowerISA mod* instructions --- diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn index 25bc3ad86..840541915 100644 --- a/openpower/sv/biginteger.mdwn +++ b/openpower/sv/biginteger.mdwn @@ -99,7 +99,7 @@ When `EXTRA2_MODE` is set to one, the implicit RS register is identical to RC extended with SVP64 using `Rsrc3_EXTRA2` in every respect, including whether RC is set Scalar or Vector. -# divrem2du RT,RA,RB,RC +# divmod2du RT,RA,RB,RC **DRAFT** @@ -145,9 +145,9 @@ Pseudo-code: For the Opcode map (XO Field) see Power ISA v3.1, Book III, Appendix D, Table 13 (sheet 7 of 8), p1357. Proposed is the addition of `madded` (**DRAFT, NOT APPROVED**) in `110010` -and `divrem2du` in `110100` +and `divmod2du` in `110100` |110000|110001 |110010 |110011|110100 |110101|110110|110111| |------|-------|----------|------|-------------|------|------|------| -|maddhd|maddhdu|**madded**|maddld|**divrem2du**|rsvd |rsvd |rsvd | +|maddhd|maddhdu|**madded**|maddld|**divmod2du**|rsvd |rsvd |rsvd | diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn index 5e03e1f2b..7ff374a84 100644 --- a/openpower/sv/biginteger/analysis.mdwn +++ b/openpower/sv/biginteger/analysis.mdwn @@ -7,7 +7,7 @@ * Revision 0.0: 21apr2022 * Revision 0.01: 22apr2022 removal of msubed because sv.madded and sv.subfe works * Revision 0.02: 22apr2022 128/64 scalar divide, investigate Goldschmidt -* Revision 0.03: 24apr2022 add 128/64 divrem2du, similar loop to madded +* Revision 0.03: 24apr2022 add 128/64 divmod2du, similar loop to madded * Revision 0.04: 26apr2022 Knuth original uses overflow on scalar div * Revision 0.05: 27apr2022 add vector shift section (no new instructions) @@ -504,7 +504,7 @@ produce both the quotient and the remainder. The pseudocode cleanly covering both scenarios (leaving out overflow for clarity) can be written as: -`divrem2du RT,RA,RB,RC` +`divmod2du RT,RA,RB,RC` dividend = (RC) || (RA) divisor = EXTZ128(RB) @@ -535,7 +535,7 @@ detection is required. When the divisor is too small compared to the dividend then the result may not fit into 64 bit. Knuth's original algorithm detects overflow and manually places 0xffffffff (all ones) into `qhat`. With there being so many operands already -in `divrem2du` a `cmpl` instruction can be used instead to detect +in `divmod2du` a `cmpl` instruction can be used instead to detect the overflow. This saves having to add an Rc=1 or OE=1 mode when the available space in VA-Form EXT04 is extremely limited.