From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 17 Sep 2022 15:53:28 +0000 (+0100)
Subject: add vec2/3/4 test_pysvp64dis test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2fbdc7f20190afaa98a504708ae2114107f765e4;p=openpower-isa.git

add vec2/3/4 test_pysvp64dis test
---

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index 44ebf136..9f89edfb 100644
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -172,6 +172,14 @@ class SVSTATETestCase(unittest.TestCase):
         dis = lambda entry: sv_binutils_fptrans.dis(entry, binutils=False)
         self._do_tst(list(map(dis, entries)))
 
+    def test_10_vec(self):
+        expected = [
+                    "sv.add./vec2 *3,*7,*11",
+                    "sv.add./vec3 *3,*7,*11",
+                    "sv.add./vec4 *3,*7,*11",
+                        ]
+        self._do_tst(expected)
+
 if __name__ == "__main__":
     unittest.main()