From: whitequark Date: Fri, 21 Dec 2018 23:53:18 +0000 (+0000) Subject: hdl.ir: fix port propagation between siblings. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2fc2461c0ad17a9cd085ab2398813a6cf4e2214e;p=nmigen.git hdl.ir: fix port propagation between siblings. --- diff --git a/nmigen/hdl/ir.py b/nmigen/hdl/ir.py index 018fa9a..1d6a79f 100644 --- a/nmigen/hdl/ir.py +++ b/nmigen/hdl/ir.py @@ -270,9 +270,9 @@ class Fragment: # Go through subfragments and refine our approximation for ports. for subfrag, name in self.subfragments: - # Always ask subfragments to provide all signals we're using and signals we're asked - # to provide. If the subfragment is not driving it, it will silently ignore it. - sub_ins, sub_outs, sub_inouts = subfrag._propagate_ports(ports=self_used | ports) + # Always ask subfragments to provide all signals that are our inputs. + # If the subfragment is not driving it, it will silently ignore it. + sub_ins, sub_outs, sub_inouts = subfrag._propagate_ports(ports=ins | ports) # Refine the input port approximation: if a subfragment is driving a signal, # it is definitely not our input. But, if a subfragment requires a signal as an input, # and we aren't driving it, it has to be our input as well. diff --git a/nmigen/test/test_hdl_ir.py b/nmigen/test/test_hdl_ir.py index bd71eca..06c45e3 100644 --- a/nmigen/test/test_hdl_ir.py +++ b/nmigen/test/test_hdl_ir.py @@ -117,6 +117,23 @@ class FragmentPortsTestCase(FHDLTestCase): (self.c2, "o"), ])) + def test_input_output_sibling(self): + f1 = Fragment() + f2 = Fragment() + f2.add_statements( + self.c1.eq(self.c2) + ) + f1.add_subfragment(f2) + f3 = Fragment() + f3.add_statements( + self.c2.eq(0) + ) + f3.add_driver(self.c2) + f1.add_subfragment(f3) + + f1._propagate_ports(ports=()) + self.assertEqual(f1.ports, SignalDict()) + def test_input_cd(self): sync = ClockDomain() f = Fragment()