From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 18 Mar 2015 13:41:43 +0000 (+0100)
Subject: migen/genlib/io: use 0 instead of Signal() for default rst value (immutable thanks sb)
X-Git-Tag: 24jan2021_ls180~2099^2~166
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2fc2f8a6c076658c024bfa785c5bbe30597b582b;p=litex.git

migen/genlib/io: use 0 instead of Signal() for default rst value (immutable thanks sb)
---

diff --git a/migen/genlib/io.py b/migen/genlib/io.py
index cd436072..ab8cc9bf 100644
--- a/migen/genlib/io.py
+++ b/migen/genlib/io.py
@@ -35,7 +35,7 @@ class DifferentialOutput(Special):
 		raise NotImplementedError("Attempted to use a differential output, but platform does not support them")
 
 class CRG(Module):
-	def __init__(self, clk, rst=Signal()):
+	def __init__(self, clk, rst=0):
 		self.clock_domains.cd_sys = ClockDomain()
 		self.clock_domains.cd_por = ClockDomain(reset_less=True)