From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 16 Oct 2018 22:40:26 +0000 (+0100)
Subject: shuffle CSR offsets around, offset VL and MVL by one
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2fc641682d7f4ead08ddd7feb53bd6428283e57e;p=riscv-isa-sim.git

shuffle CSR offsets around, offset VL and MVL by one

VL and MVL now span from 1 to XLEN rather than 0 to XLEN-1

also making room for M-Mode and S-Mode CSRs
---

diff --git a/riscv/encoding.h b/riscv/encoding.h
index 19b28c4..ae66637 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -908,9 +908,16 @@
 #define CSR_SVPREDCFG5 0x4cd
 #define CSR_SVPREDCFG6 0x4ce
 #define CSR_SVPREDCFG7 0x4cf
-#define CSR_SVVL 0x4f0
-#define CSR_SVSTATE 0x4f1
-#define CSR_SVMVL 0x4f2
+#define CSR_MSVVL 0x4d0
+#define CSR_MSVMVL 0x4d1
+#define CSR_MSVSTATE 0x4d2
+#define CSR_SSVVL 0x4e0
+#define CSR_SSVMVL 0x4e1
+#define CSR_SSVSTATE 0x4e2
+#define CSR_USVVL 0x4f0
+#define CSR_USVMVL 0x4f1
+#define CSR_USVSTATE 0x4f2
+#define CSR_USVCFG 0x4f3
 #define CSR_MVENDORID 0xf11
 #define CSR_MARCHID 0xf12
 #define CSR_MIMPID 0xf13
@@ -1259,9 +1266,16 @@ DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
 DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
 #endif
 #ifdef DECLARE_CSR
-DECLARE_CSR(svvl, CSR_SVVL)
-DECLARE_CSR(svstate, CSR_SVSTATE)
-DECLARE_CSR(svmvl, CSR_SVMVL)
+DECLARE_CSR(msvvl, CSR_MSVVL)
+DECLARE_CSR(msvmvl, CSR_MSVMVL)
+DECLARE_CSR(msvstate, CSR_MSVSTATE)
+DECLARE_CSR(ssvvl, CSR_SSVVL)
+DECLARE_CSR(ssvmvl, CSR_SSVMVL)
+DECLARE_CSR(ssvstate, CSR_SSVSTATE)
+DECLARE_CSR(usvcfg, CSR_USVCFG)
+DECLARE_CSR(usvstate, CSR_USVSTATE)
+DECLARE_CSR(usvvl, CSR_USVVL)
+DECLARE_CSR(usvmvl, CSR_USVMVL)
 DECLARE_CSR(svregcfg0, CSR_SVREGCFG0)
 DECLARE_CSR(svregcfg1, CSR_SVREGCFG1)
 DECLARE_CSR(svregcfg2, CSR_SVREGCFG2)
diff --git a/riscv/insns/csrrw.h b/riscv/insns/csrrw.h
index 6bc1df8..7fb87e9 100644
--- a/riscv/insns/csrrw.h
+++ b/riscv/insns/csrrw.h
@@ -1,12 +1,12 @@
 int csr = validate_csr(insn.csr(), true);
 #ifdef SPIKE_SIMPLEV
 reg_t old = 0; // stop compiler bitchin
-if (csr != CSR_SVVL)
+if (csr != CSR_USVVL && csr != CSR_USVMVL)
 {
     old = p->get_csr(csr);
 }
 p->set_csr(csr, RS1);
-if (csr == CSR_SVVL)
+if (csr == CSR_USVVL || csr == CSR_USVMVL)
 {
     old = p->get_csr(csr);
 }
diff --git a/riscv/insns/csrrwi.h b/riscv/insns/csrrwi.h
index 7b70600..8a253ee 100644
--- a/riscv/insns/csrrwi.h
+++ b/riscv/insns/csrrwi.h
@@ -3,12 +3,12 @@ int csr = validate_csr(insn.csr(), true);
 fprintf(stderr, "validated %x\n", csr);
 #ifdef SPIKE_SIMPLEV
 reg_t old = 0; // stop compiler bitchin
-if (csr != CSR_SVVL)
+if (csr != CSR_USVVL && csr != CSR_USVMVL)
 {
     old = p->get_csr(csr);
 }
 p->set_csr(csr, insn.rs1());
-if (csr == CSR_SVVL)
+if (csr == CSR_USVVL || csr == CSR_USVMVL)
 {
     old = p->get_csr(csr);
 }
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 9aa17a8..5b73dcc 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -343,19 +343,19 @@ void processor_t::set_csr(int which, reg_t val)
   switch (which)
   {
 #ifdef SPIKE_SIMPLEV
-    case CSR_SVMVL:
-      state.mvl = std::min(val, (uint64_t)63); // limited to XLEN width
+    case CSR_USVMVL:
+      state.mvl = std::min(val+1, (uint64_t)64); // limited to XLEN width
       fprintf(stderr, "set MVL %lx\n", state.mvl);
       break;
-    case CSR_SVSTATE:
+    case CSR_USVSTATE:
       // bits 0-5: mvl - 6-11: vl - 12-17: srcoffs - 18-23: destoffs
-      set_csr(CSR_SVMVL, get_field(val, 0x1f));
-      set_csr(CSR_SVVL , get_field(val, 0x1f<<6));
-      state.srcoffs = std::min(get_field(val, 0x1f<<12), state.vl);
-      state.destoffs = std::min(get_field(val, 0x1f<<18), state.vl);
+      set_csr(CSR_USVMVL, get_field(val, 0x1f));
+      set_csr(CSR_USVVL , get_field(val, 0x1f<<6));
+      state.srcoffs = std::min(get_field(val, 0x1f<<12), state.vl-1);
+      state.destoffs = std::min(get_field(val, 0x1f<<18), state.vl-1);
       break;
-    case CSR_SVVL:
-      state.vl = std::min(state.mvl, val);
+    case CSR_USVVL:
+      state.vl = std::min(state.mvl, val+1);
       fprintf(stderr, "set VL %lx\n", state.vl);
       break;
     case CSR_SVREGCFG0:
@@ -686,12 +686,12 @@ reg_t processor_t::get_csr(int which)
   switch (which)
   {
 #ifdef SPIKE_SIMPLEV
-    case CSR_SVVL:
+    case CSR_USVVL:
       return state.vl;
-    case CSR_SVSTATE:
-      return state.vl            | (state.mvl<<6) |
-             (state.srcoffs<<12) | (state.destoffs<<18) ;
-    case CSR_SVMVL:
+    case CSR_USVSTATE:
+      return (state.vl-1)            | ((state.mvl-1)<<6) |
+             (state.srcoffs<<12)     | (state.destoffs<<18) ;
+    case CSR_USVMVL:
       return state.mvl;
     case CSR_SVREGCFG0:
     case CSR_SVREGCFG1: