From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sat, 22 Sep 2012 18:50:49 +0000 (+0200)
Subject: fhdl: support inverted clock ports in instances
X-Git-Tag: 24jan2021_ls180~2099^2~834
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2fc9cae88a0b553268798c8004c13ed809d190f9;p=litex.git

fhdl: support inverted clock ports in instances
---

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 6b77840b..27d7bdcb 100644
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -274,9 +274,10 @@ class Instance:
 			self.value = value
 	
 	class _CR:
-		def __init__(self, name_inst, domain="sys"):
+		def __init__(self, name_inst, domain="sys", invert=False):
 			self.name_inst = name_inst
 			self.domain = domain
+			self.invert = invert
 	class ClockPort(_CR):
 		pass
 	class ResetPort(_CR):
diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index d0cbecf8..e48875f7 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -210,6 +210,8 @@ def _printinstances(f, ns, clock_domains):
 			elif isinstance(p, Instance.ClockPort):
 				name_inst = p.name_inst
 				name_design = ns.get_name(clock_domains[p.domain].clk)
+				if p.invert:
+					name_design = "~" + name_design
 			elif isinstance(p, Instance.ResetPort):
 				name_inst = p.name_inst
 				name_design = ns.get_name(clock_domains[p.domain].rst)