From: Dmitry Selyutin Date: Thu, 8 Sep 2022 21:04:37 +0000 (+0300) Subject: power_insn: deprecate redundant else section X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3009e99a139f7dffb6306381d358c95c3fb5f5d4;p=openpower-isa.git power_insn: deprecate redundant else section --- diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index 35712cab..bd1f5a91 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -540,6 +540,31 @@ class DynamicOperand(Operand): yield str(int(value)) +@_dataclasses.dataclass(eq=True, frozen=True) +class ImmediateOperand(DynamicOperand): + pass + + +@_dataclasses.dataclass(eq=True, frozen=True) +class StaticOperand(Operand): + value: int + + def disassemble(self, insn, record, + verbosity=Verbosity.NORMAL, indent=""): + span = record.fields[self.name] + if isinstance(insn, SVP64Instruction): + span = tuple(map(lambda bit: (bit + 32), span)) + value = insn[span] + + if verbosity >= Verbosity.VERBOSE: + span = map(str, span) + yield f"{indent}{self.name}" + yield f"{indent}{indent}{int(value):0{value.bits}b}" + yield f"{indent}{indent}{', '.join(span)}" + else: + yield str(int(value)) + + @_dataclasses.dataclass(eq=True, frozen=True) class DynamicOperandReg(DynamicOperand): def spec(self, insn, record): @@ -589,9 +614,6 @@ class DynamicOperandReg(DynamicOperand): value = _SelectableInt(value=value, bits=bits) - else: - value = insn[span] - span = tuple(map(str, span)) return (vector, value, span) @@ -633,29 +655,23 @@ class DynamicOperandReg(DynamicOperand): yield f"{vector}{prefix}{int(value)}" -@_dataclasses.dataclass(eq=True, frozen=True) -class ImmediateOperand(DynamicOperand): - pass +class DynamicOperandGPR(DynamicOperandReg): + def disassemble(self, insn, record, + verbosity=Verbosity.NORMAL, indent=""): + prefix = "" if (verbosity <= Verbosity.SHORT) else "r" + yield from super().disassemble(prefix=prefix, + insn=insn, record=record, + verbosity=verbosity, indent=indent) @_dataclasses.dataclass(eq=True, frozen=True) -class StaticOperand(Operand): - value: int - +class DynamicOperandFPR(DynamicOperandReg): def disassemble(self, insn, record, verbosity=Verbosity.NORMAL, indent=""): - span = record.fields[self.name] - if isinstance(insn, SVP64Instruction): - span = tuple(map(lambda bit: (bit + 32), span)) - value = insn[span] - - if verbosity >= Verbosity.VERBOSE: - span = map(str, span) - yield f"{indent}{self.name}" - yield f"{indent}{indent}{int(value):0{value.bits}b}" - yield f"{indent}{indent}{', '.join(span)}" - else: - yield str(int(value)) + prefix = "" if (verbosity <= Verbosity.SHORT) else "f" + yield from super().disassemble(prefix=prefix, + insn=insn, record=record, + verbosity=verbosity, indent=indent) @_dataclasses.dataclass(eq=True, frozen=True) @@ -695,26 +711,6 @@ class DynamicOperandTargetAddrBD(DynamicOperandTargetAddr): verbosity=verbosity, indent=indent) -@_dataclasses.dataclass(eq=True, frozen=True) -class DynamicOperandGPR(DynamicOperandReg): - def disassemble(self, insn, record, - verbosity=Verbosity.NORMAL, indent=""): - prefix = "" if (verbosity <= Verbosity.SHORT) else "r" - yield from super().disassemble(prefix=prefix, - insn=insn, record=record, - verbosity=verbosity, indent=indent) - - -@_dataclasses.dataclass(eq=True, frozen=True) -class DynamicOperandFPR(DynamicOperandReg): - def disassemble(self, insn, record, - verbosity=Verbosity.NORMAL, indent=""): - prefix = "" if (verbosity <= Verbosity.SHORT) else "f" - yield from super().disassemble(prefix=prefix, - insn=insn, record=record, - verbosity=verbosity, indent=indent) - - class Operands(tuple): def __new__(cls, insn, iterable): branches = {