From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 2 Jan 2020 20:48:07 +0000 (-0800)
Subject: Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor
X-Git-Tag: working-ls180~883^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3012e9eebc2950b996d17a018bb2e0535badef22;p=yosys.git

Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor
---

3012e9eebc2950b996d17a018bb2e0535badef22
diff --cc techlibs/xilinx/cells_sim.v
index 2947fe692,c27b0f02b..7bfc36aa3
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@@ -2241,81 -2235,8 +2241,81 @@@ module DSP48E1 
      parameter [4:0] IS_INMODE_INVERTED = 5'b0;
      parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
  
 +    function \DSP48E1.P_arrival ;
 +        input USE_MULT, USE_DPORT;
 +        input AREG, ADREG, BREG, CREG, DREG, MREG, PREG;
 +    begin
 +        \DSP48E1.P_arrival = 0;
 +        if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
 +            if (PREG != 0)      \DSP48E1.P_arrival =  329;
 +            // Worse-case from CREG and MREG
 +            else if (CREG != 0) \DSP48E1.P_arrival = 1687;
 +            else if (MREG != 0) \DSP48E1.P_arrival = 1671;
 +            // Worse-case from AREG and BREG
 +            else if (AREG != 0) \DSP48E1.P_arrival = 2952;
 +            else if (BREG != 0) \DSP48E1.P_arrival = 2813;
 +        end
 +        else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
 +            if (PREG != 0)      \DSP48E1.P_arrival =  329;
 +            // Worse-case from CREG and MREG
 +            else if (CREG != 0) \DSP48E1.P_arrival = 1687;
 +            else if (MREG != 0) \DSP48E1.P_arrival = 1671;
 +            // Worse-case from AREG, ADREG, BREG, DREG
 +            else if (AREG != 0)  \DSP48E1.P_arrival = 3935;
 +            else if (DREG != 0)  \DSP48E1.P_arrival = 3908;
 +            else if (ADREG != 0) \DSP48E1.P_arrival = 2958;
 +            else if (BREG != 0)  \DSP48E1.P_arrival = 2813;
 +        end
 +        else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
 +            if (PREG != 0)      \DSP48E1.P_arrival =  329;
 +            // Worse-case from AREG, BREG, CREG
 +            else if (CREG != 0) \DSP48E1.P_arrival = 1687;
 +            else if (AREG != 0) \DSP48E1.P_arrival = 1632;
 +            else if (BREG != 0) \DSP48E1.P_arrival = 1616;
 +        end
 +        //else
 +        //    $error("Invalid DSP48E1 configuration");
 +    end
 +    endfunction
 +    function \DSP48E1.PCOUT_arrival ;
 +        input USE_MULT, USE_DPORT;
 +        input AREG, ADREG, BREG, CREG, DREG, MREG, PREG;
 +    begin
 +        \DSP48E1.PCOUT_arrival = 0;
 +        if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
 +            if (PREG != 0)      \DSP48E1.PCOUT_arrival =  435;
 +            // Worse-case from CREG and MREG
 +            else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835;
 +            else if (MREG != 0) \DSP48E1.PCOUT_arrival = 1819;
 +            // Worse-case from AREG and BREG
 +            else if (AREG != 0) \DSP48E1.PCOUT_arrival = 3098;
 +            else if (BREG != 0) \DSP48E1.PCOUT_arrival = 2960;
 +        end
 +        else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
 +            if (PREG != 0)      \DSP48E1.PCOUT_arrival =  435;
 +            // Worse-case from CREG and MREG
 +            else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835;
 +            else if (MREG != 0) \DSP48E1.PCOUT_arrival = 1819;
 +            // Worse-case from AREG, ADREG, BREG, DREG
 +            else if (AREG != 0)  \DSP48E1.PCOUT_arrival = 4083;
 +            else if (DREG != 0)  \DSP48E1.PCOUT_arrival = 4056;
 +            else if (BREG != 0)  \DSP48E1.PCOUT_arrival = 2960;
 +            else if (ADREG != 0) \DSP48E1.PCOUT_arrival = 2859;
 +        end
 +        else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
 +            if (PREG != 0)      \DSP48E1.PCOUT_arrival =  435;
 +            // Worse-case from AREG, BREG, CREG
 +            else if (CREG != 0) \DSP48E1.PCOUT_arrival = 1835;
 +            else if (AREG != 0) \DSP48E1.PCOUT_arrival = 1780;
 +            else if (BREG != 0) \DSP48E1.PCOUT_arrival = 1765;
 +        end
 +        //else
 +        //    $error("Invalid DSP48E1 configuration");
 +    end
 +    endfunction
 +
      initial begin
- `ifdef __ICARUS__
+ `ifndef YOSYS
          if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value");
          if (SEL_MASK != "MASK")     $fatal(1, "Unsupported SEL_MASK value");
          if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value");