From: Eric Anholt Date: Fri, 7 Mar 2014 00:29:39 +0000 (-0800) Subject: i965: Move binding table update packets to binding table setup time. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=30259856a8a82a55c030df1ad052e505c61144bc;p=mesa.git i965: Move binding table update packets to binding table setup time. This keeps us from needing to reemit all the other stage state just because a surface changed. Improves unoptimized glamor x11perf -f8text by 1.10201% +/- 0.489869% (n=296). [v1] v2: - Drop binding table packets from Gen8 unit state as well. - Pass _3DSTATE_BINDING_TABLE_POINTERS_XS to brw_upload_binding_table, cutting even more code. v3: Don't forget to drop them from 3DSTATE_GS (botched refactor in v2). Signed-off-by: Eric Anholt [v1] Reviewed-by: Kenneth Graunke [v1] Signed-off-by: Kenneth Graunke [v2, v3] Reviewed-by: Eric Anholt [v3] --- diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c b/src/mesa/drivers/dri/i965/brw_binding_tables.c index 0de5d1a0737..1cd4bba6753 100644 --- a/src/mesa/drivers/dri/i965/brw_binding_tables.c +++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c @@ -52,6 +52,7 @@ */ static void brw_upload_binding_table(struct brw_context *brw, + uint32_t packet_name, GLbitfield brw_new_binding_table, struct brw_stage_state *stage_state) { @@ -82,6 +83,13 @@ brw_upload_binding_table(struct brw_context *brw, } brw->state.dirty.brw |= brw_new_binding_table; + + if (brw->gen >= 7) { + BEGIN_BATCH(2); + OUT_BATCH(packet_name << 16 | (2 - 2)); + OUT_BATCH(stage_state->bind_bo_offset); + ADVANCE_BATCH(); + } } /** @@ -93,7 +101,9 @@ brw_upload_binding_table(struct brw_context *brw, static void brw_vs_upload_binding_table(struct brw_context *brw) { - brw_upload_binding_table(brw, BRW_NEW_VS_BINDING_TABLE, &brw->vs.base); + brw_upload_binding_table(brw, + _3DSTATE_BINDING_TABLE_POINTERS_VS, + BRW_NEW_VS_BINDING_TABLE, &brw->vs.base); } const struct brw_tracked_state brw_vs_binding_table = { @@ -112,7 +122,9 @@ const struct brw_tracked_state brw_vs_binding_table = { static void brw_upload_wm_binding_table(struct brw_context *brw) { - brw_upload_binding_table(brw, BRW_NEW_PS_BINDING_TABLE, &brw->wm.base); + brw_upload_binding_table(brw, + _3DSTATE_BINDING_TABLE_POINTERS_PS, + BRW_NEW_PS_BINDING_TABLE, &brw->wm.base); } const struct brw_tracked_state brw_wm_binding_table = { @@ -132,7 +144,9 @@ brw_gs_upload_binding_table(struct brw_context *brw) if (brw->geometry_program == NULL) return; - brw_upload_binding_table(brw, BRW_NEW_GS_BINDING_TABLE, &brw->gs.base); + brw_upload_binding_table(brw, + _3DSTATE_BINDING_TABLE_POINTERS_GS, + BRW_NEW_GS_BINDING_TABLE, &brw->gs.base); } const struct brw_tracked_state brw_gs_binding_table = { diff --git a/src/mesa/drivers/dri/i965/gen7_gs_state.c b/src/mesa/drivers/dri/i965/gen7_gs_state.c index b179d1954b1..d18ae155185 100644 --- a/src/mesa/drivers/dri/i965/gen7_gs_state.c +++ b/src/mesa/drivers/dri/i965/gen7_gs_state.c @@ -66,12 +66,6 @@ upload_gs_state(struct brw_context *brw) /* CACHE_NEW_GS_PROG */ const struct brw_vec4_prog_data *prog_data = &brw->gs.prog_data->base; - /* BRW_NEW_GS_BINDING_TABLE */ - BEGIN_BATCH(2); - OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_GS << 16 | (2 - 2)); - OUT_BATCH(stage_state->bind_bo_offset); - ADVANCE_BATCH(); - /* CACHE_NEW_SAMPLER */ BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_GS << 16 | (2 - 2)); diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c index c4f1d264bff..0d9859bec59 100644 --- a/src/mesa/drivers/dri/i965/gen7_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c @@ -75,12 +75,6 @@ upload_vs_state(struct brw_context *brw) if (!brw->is_haswell) gen7_emit_vs_workaround_flush(brw); - /* BRW_NEW_VS_BINDING_TABLE */ - BEGIN_BATCH(2); - OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_VS << 16 | (2 - 2)); - OUT_BATCH(stage_state->bind_bo_offset); - ADVANCE_BATCH(); - /* CACHE_NEW_SAMPLER */ BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_VS << 16 | (2 - 2)); diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index 38067e60c8b..ca3e2753935 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c @@ -143,12 +143,6 @@ upload_ps_state(struct brw_context *brw) const int max_threads_shift = brw->is_haswell ? HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT; - /* BRW_NEW_PS_BINDING_TABLE */ - BEGIN_BATCH(2); - OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2)); - OUT_BATCH(brw->wm.base.bind_bo_offset); - ADVANCE_BATCH(); - /* CACHE_NEW_SAMPLER */ BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2)); diff --git a/src/mesa/drivers/dri/i965/gen8_gs_state.c b/src/mesa/drivers/dri/i965/gen8_gs_state.c index c018d7084fb..97fbf84f7ff 100644 --- a/src/mesa/drivers/dri/i965/gen8_gs_state.c +++ b/src/mesa/drivers/dri/i965/gen8_gs_state.c @@ -36,12 +36,6 @@ gen8_upload_gs_state(struct brw_context *brw) /* CACHE_NEW_GS_PROG */ const struct brw_vec4_prog_data *prog_data = &brw->gs.prog_data->base; - /* BRW_NEW_GS_BINDING_TABLE */ - BEGIN_BATCH(2); - OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_GS << 16 | (2 - 2)); - OUT_BATCH(stage_state->bind_bo_offset); - ADVANCE_BATCH(); - /* CACHE_NEW_SAMPLER */ BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_GS << 16 | (2 - 2)); diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c index 561fc96e7d3..7d8f9544ee6 100644 --- a/src/mesa/drivers/dri/i965/gen8_ps_state.c +++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c @@ -136,12 +136,6 @@ upload_ps_state(struct brw_context *brw) struct gl_context *ctx = &brw->ctx; uint32_t dw3 = 0, dw6 = 0, dw7 = 0; - /* BRW_NEW_PS_BINDING_TABLE */ - BEGIN_BATCH(2); - OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2)); - OUT_BATCH(brw->wm.base.bind_bo_offset); - ADVANCE_BATCH(); - /* CACHE_NEW_SAMPLER */ BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2)); diff --git a/src/mesa/drivers/dri/i965/gen8_vs_state.c b/src/mesa/drivers/dri/i965/gen8_vs_state.c index 02a0176a702..373cfe4b6f8 100644 --- a/src/mesa/drivers/dri/i965/gen8_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen8_vs_state.c @@ -62,12 +62,6 @@ upload_vs_state(struct brw_context *brw) /* CACHE_NEW_VS_PROG */ const struct brw_vec4_prog_data *prog_data = &brw->vs.prog_data->base; - /* BRW_NEW_VS_BINDING_TABLE */ - BEGIN_BATCH(2); - OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_VS << 16 | (2 - 2)); - OUT_BATCH(stage_state->bind_bo_offset); - ADVANCE_BATCH(); - /* CACHE_NEW_SAMPLER */ BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_VS << 16 | (2 - 2));