From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 15 Jun 2021 15:36:59 +0000 (+0100)
Subject: add fmadds and fmsubs to Power ISA pseudo-code, add unit test (scalar)
X-Git-Tag: xlen-bcd~456
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3036565f07739dacc11b6c23cdd2566914a905d7;p=openpower-isa.git

add fmadds and fmsubs to Power ISA pseudo-code, add unit test (scalar)
---

diff --git a/openpower/isa/fparith.mdwn b/openpower/isa/fparith.mdwn
index 2ce6a2cd..1c80d0e1 100644
--- a/openpower/isa/fparith.mdwn
+++ b/openpower/isa/fparith.mdwn
@@ -145,3 +145,40 @@ Special Registers Altered:
     FX OX UX XX
     VXSNAN VXISI
     CR1          (if Rc=1)
+
+# Floating Multiply-Add [Single]
+
+A-Form
+
+* fmadds FRT,FRA,FRC,FRB (Rc=0)
+* fmadds. FRT,FRA,FRC,FRB (Rc=0)
+
+Pseudo-code:
+
+    FRT <- FPMULADD32(FRA, FRC, FRB, 1)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)
+
+# Floating Multiply-Sub [Single]
+
+A-Form
+
+* fmsubs FRT,FRA,FRC,FRB (Rc=0)
+* fmsubs. FRT,FRA,FRC,FRB (Rc=0)
+
+Pseudo-code:
+
+    FRT <- FPMULADD32(FRA, FRC, FRB, -1)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)
+
diff --git a/src/openpower/decoder/helpers.py b/src/openpower/decoder/helpers.py
index e9406070..5440217f 100644
--- a/src/openpower/decoder/helpers.py
+++ b/src/openpower/decoder/helpers.py
@@ -287,6 +287,26 @@ def FPMUL32(FRA, FRB):
     return cvt
 
 
+def FPMULADD32(FRA, FRB, FRC, sign):
+    from openpower.decoder.isafunctions.double2single import DOUBLE2SINGLE
+    #return FPMUL64(FRA, FRB)
+    #FRA = DOUBLE(SINGLE(FRA))
+    #FRB = DOUBLE(SINGLE(FRB))
+    if sign == 1:
+        result = float(FRA) * float(FRB) + float(FRC)
+    elif sign == -1:
+        result = float(FRA) * float(FRB) - float(FRC)
+    elif sign == 0:
+        result = float(FRA) * float(FRB)
+    log ("FPMULADD32", FRA, FRB, FRC,
+                       float(FRA), float(FRB), float(FRC),
+                       result)
+    cvt = fp64toselectable(result)
+    cvt = DOUBLE2SINGLE(cvt)
+    log ("      cvt", cvt)
+    return cvt
+
+
 def FPDIV32(FRA, FRB):
     #return FPDIV64(FRA, FRB)
     #FRA = DOUBLE(SINGLE(FRA))
diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index bdb9351e..cc87701a 100644
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -211,21 +211,6 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64))
             self.assertEqual(sim.fpr(3), SelectableInt(0xc051266640000000, 64))
 
-    def test_fp_muls2(self):
-        """>>> lst = ["fmuls 3, 1, 2",
-                     ]
-        """
-        lst = ["fmuls 3, 1, 2", #
-                     ]
-
-        fprs = [0] * 32
-        fprs[1] = 0xbfc4e9d700000000
-        fprs[2] = 0xbdc5000000000000
-
-        with Program(lst, bigendian=False) as program:
-            sim = self.run_tst_program(program, initial_fprs=fprs)
-            self.assertEqual(sim.fpr(3), SelectableInt(0x3d9b72ea40000000, 64))
-
     def test_fp_muls3(self):
         """>>> lst = ["fmuls 3, 1, 2",
                      ]
@@ -289,6 +274,38 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64))
             self.assertEqual(sim.fpr(3), SelectableInt(0xC051266666666667, 64))
 
+    def test_fp_madd1(self):
+        """>>> lst = ["fmadds 3, 1, 2, 4",
+                     ]
+        """
+        lst = ["fmadds 3, 1, 2, 4", # 7.0 * -9.8 + 2 = -66.6
+                     ]
+
+        fprs = [0] * 32
+        fprs[1] = 0x401C000000000000  # 7.0
+        fprs[2] = 0xC02399999999999A  # -9.8
+        fprs[4] = 0x4000000000000000  # 2.0
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_fprs=fprs)
+            self.assertEqual(sim.fpr(3), SelectableInt(0xC050A66660000000, 64))
+
+    def test_fp_msub1(self):
+        """>>> lst = ["fmsubs 3, 1, 2, 4",
+                     ]
+        """
+        lst = ["fmsubs 3, 1, 2, 4", # 7.0 * -9.8 + 2 = -70.6
+                     ]
+
+        fprs = [0] * 32
+        fprs[1] = 0x401C000000000000  # 7.0
+        fprs[2] = 0xC02399999999999A  # -9.8
+        fprs[4] = 0x4000000000000000  # 2.0
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_fprs=fprs)
+            self.assertEqual(sim.fpr(3), SelectableInt(0xc051a66660000000, 64))
+
     def test_fp_fcfids(self):
         """>>> lst = ["fcfids 1, 2",
                lst = ["fcfids 3, 4",
diff --git a/src/openpower/decoder/pseudo/pywriter.py b/src/openpower/decoder/pseudo/pywriter.py
index 0ba05007..766f7929 100644
--- a/src/openpower/decoder/pseudo/pywriter.py
+++ b/src/openpower/decoder/pseudo/pywriter.py
@@ -40,6 +40,7 @@ from openpower.decoder.helpers import (
                                  DOUBLE, SINGLE,
                                  FPADD32, FPSUB32, FPMUL32, FPDIV32,
                                  FPADD64, FPSUB64, FPMUL64, FPDIV64,
+                                 FPMULADD32,
                                 )
 from openpower.decoder.isafunctions.fpfromint import INT2FP