From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 14 Feb 2019 15:10:44 +0000 (+0000)
Subject: corrections
X-Git-Tag: ls180-24jan2020~1989
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=30392515cf6c026ffaeb6f00f4bc8773d354cbc8;p=ieee754fpu.git

corrections
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 60fae193..f0f3f735 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -195,12 +195,12 @@ class FPADD:
                     with m.If(a.e == -127):
                         m.d.sync += a.e.eq(-126) # limit a exponent
                     with m.Else():
-                        m.d.sync += a.m[26].eq(1) # set highest mantissa bit
+                        m.d.sync += a.m[26].eq(1) # set top mantissa bit
                     # denormalise b check
                     with m.If(b.e == -127):
                         m.d.sync += b.e.eq(-126) # limit b exponent
                     with m.Else():
-                        m.d.sync += b.m[26].eq(1) # set highest mantissa bit
+                        m.d.sync += b.m[26].eq(1) # set top mantissa bit
 
             # ******
             # align.  NOTE: this does *not* do single-cycle multi-shifting,
@@ -309,7 +309,7 @@ class FPADD:
             # rounding stage
 
             with m.State("round"):
-                m.next = "correction"
+                m.next = "corrections"
                 with m.If(guard & (round_bit | sticky | z.m[0])):
                     m.d.sync += z.m.eq(z.m + 1) # mantissa rounds up
                     with m.If(z.m == 0xffffff): # all 1s