From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 9 Mar 2020 15:41:11 +0000 (+0000)
Subject: try adding test memory store to LDSTCompUnit
X-Git-Tag: div_pipeline~1741
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=303b5767e72bb7cd64f9b5899404a7082749782c;p=soc.git

try adding test memory store to LDSTCompUnit
---

diff --git a/src/soc/experiment/compldst.py b/src/soc/experiment/compldst.py
index 77ad39dd..6af98f5a 100644
--- a/src/soc/experiment/compldst.py
+++ b/src/soc/experiment/compldst.py
@@ -1,9 +1,3 @@
-from nmigen.compat.sim import run_simulation
-from nmigen.cli import verilog, rtlil
-from nmigen import Module, Signal, Mux, Cat, Elaboratable
-
-from nmutil.latch import SRLatch, latchregister
-
 """ LOAD / STORE Computation Unit.  Also capable of doing ADD and ADD immediate
 
     This module runs a "revolving door" set of four latches, based on
@@ -14,18 +8,34 @@ from nmutil.latch import SRLatch, latchregister
 
     (Note that opc_l has been inverted (and qn used), due to SRLatch
      default reset state being "0" rather than "1")
+
+    Also note: the LD/ST Comp Unit can act as a *standard ALU* doing
+    add and subtract.
+
+    Stores are activated when Go_Store is enabled, and uses the ALU
+    to add the immediate (imm_i) to the address (src1_i), and then
+    when ready (go_st_i and the ALU ready) the operand (src2_i) is stored
+    in the computed address.
 """
 
+from nmigen.compat.sim import run_simulation
+from nmigen.cli import verilog, rtlil
+from nmigen import Module, Signal, Mux, Cat, Elaboratable
+
+from nmutil.latch import SRLatch, latchregister
+
+from testmem import TestMemory
+
 # internal opcodes.  hypothetically this could do more combinations.
 # meanings:
 # * bit 0: 0 = ADD , 1 = SUB
 # * bit 1: 0 = src1, 1 = IMM
 # * bit 2: 1 = LD
 # * bit 3: 1 = ST
-LDST_OP_ADDI = 0b0000 # plain ADD (src1 + src2)
-LDST_OP_SUBI = 0b0001 # plain SUB (src1 - src2)
-LDST_OP_ADD  = 0b0010 # immed ADD (imm + src1)
-LDST_OP_SUB  = 0b0011 # immed SUB (imm - src1)
+LDST_OP_ADD  = 0b0000 # plain ADD (src1 + src2) - use this ALU as an ADD
+LDST_OP_SUB  = 0b0001 # plain SUB (src1 - src2) - use this ALU as a SUB
+LDST_OP_ADDI = 0b0010 # immed ADD (imm + src1)
+LDST_OP_SUBI = 0b0011 # immed SUB (imm - src1)
 LDST_OP_ST   = 0b0110 # immed ADD plus LD op.  ADD result is address
 LDST_OP_LD   = 0b1010 # immed ADD plus ST op.  ADD result is address
 
@@ -92,6 +102,7 @@ class LDSTCompUnit(Elaboratable):
         sync = m.d.sync
 
         m.submodules.alu = self.alu
+        #m.submodules.mem = self.mem
         m.submodules.src_l = src_l = SRLatch(sync=False)
         m.submodules.opc_l = opc_l = SRLatch(sync=False)
         m.submodules.adr_l = adr_l = SRLatch(sync=False)
@@ -119,6 +130,9 @@ class LDSTCompUnit(Elaboratable):
         op_ldst = Signal(reset_less=True)
         op_is_imm = Signal(reset_less=True)
 
+        # src2 register
+        src2_r = Signal(self.rwid, reset_less=True)
+
         # select immediate or src2 reg to add
         src2_or_imm = Signal(self.rwid, reset_less=True)
         src_sel = Signal(reset_less=True)
@@ -184,6 +198,7 @@ class LDSTCompUnit(Elaboratable):
 
         # create a latch/register for src1/src2 (include immediate select)
         latchregister(m, self.src1_i, self.alu.a, src_l.q)
+        latchregister(m, self.src2_i, src2_r, src_l.q)
         latchregister(m, src2_or_imm, self.alu.b, src_sel)
 
         # create a latch/register for the operand
@@ -222,6 +237,14 @@ class LDSTCompUnit(Elaboratable):
         with m.If(self.go_ad_i):
             comb += self.addr_o.eq(data_r)
 
+        # TODO: think about moving this to another module
+        # connect ST to memory
+        with m.If(self.stwd_mem_o):
+            wrport = self.mem.wrport
+            comb += wrport.addr.eq(self.addr_o)
+            comb += wrport.data.eq(src2_r)
+            comb += wrport.en.eq(1)
+
         return m
 
     def __iter__(self):
@@ -273,11 +296,23 @@ def scoreboard_sim(dut):
     yield
 
 
+class TestLDSTCompUnit(LDSTCompUnit):
+
+    def __init__(self, rwid, opwid):
+        from alu_hier import ALU
+        self.alu = alu = ALU(rwid)
+        self.mem = mem = TestMemory(rwid, 8)
+        LDSTCompUnit.__init__(self, rwid, opwid, alu, mem)
+
+    def elaborate(self, platform):
+        m = LDSTCompUnit.elaborate(self, platform)
+        m.submodules.mem = self.mem
+        return m
+
+
 def test_scoreboard():
-    from alu_hier import ALU
-    alu = ALU(16)
-    mem = alu # fake
-    dut = LDSTCompUnit(16, 4, alu, mem)
+
+    dut = TestLDSTCompUnit(16, 4)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_ldst_comp.il", "w") as f:
         f.write(vl)
diff --git a/src/soc/experiment/score6600.py b/src/soc/experiment/score6600.py
index ee4a4cd5..f720ecfb 100644
--- a/src/soc/experiment/score6600.py
+++ b/src/soc/experiment/score6600.py
@@ -15,6 +15,7 @@ from soc.scoreboard.memfu import MemFunctionUnits
 
 from compalu import ComputationUnitNoDelay
 from compldst import LDSTCompUnit
+from testmem import TestMemory
 
 from alu_hier import ALU, BranchALU
 from nmutil.latch import SRLatch
@@ -25,19 +26,6 @@ from copy import deepcopy
 from math import log
 
 
-class TestMemory(Elaboratable):
-    def __init__(self, regwid, addrw):
-        self.ddepth = 1 # regwid //8
-        depth = (1<<addrw) // self.ddepth
-        self.mem   = Memory(width=regwid, depth=depth, init=range(0, depth))
-
-    def elaborate(self, platform):
-        m = Module()
-        m.submodules.rdport = self.rdport = self.mem.read_port()
-        m.submodules.wrport = self.wrport = self.mem.write_port()
-        return m
-
-
 class MemSim:
     def __init__(self, regwid, addrw):
         self.regwid = regwid
@@ -464,7 +452,7 @@ class Scoreboard(Elaboratable):
 
         # LDST Comp Units
         n_ldsts = 2
-        cul = CompUnitLDSTs(self.rwid, 4, self.lsissue.n_insns, None)
+        cul = CompUnitLDSTs(self.rwid, 4, self.lsissue.n_insns, self.mem)
 
         # Comp Units
         m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cul, cub])
@@ -1280,7 +1268,7 @@ def scoreboard_sim(dut, alusim):
 def test_scoreboard():
     dut = IssueToScoreboard(2, 1, 1, 16, 8, 8)
     alusim = RegSim(16, 8)
-    memsim = MemSim(16, 16)
+    memsim = MemSim(16, 8)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_scoreboard6600.il", "w") as f:
         f.write(vl)
diff --git a/src/soc/experiment/testmem.py b/src/soc/experiment/testmem.py
new file mode 100644
index 00000000..848bab7b
--- /dev/null
+++ b/src/soc/experiment/testmem.py
@@ -0,0 +1,16 @@
+from nmigen import Module, Elaboratable, Memory
+
+
+class TestMemory(Elaboratable):
+    def __init__(self, regwid, addrw):
+        self.ddepth = 1 # regwid //8
+        depth = (1<<addrw) // self.ddepth
+        self.mem   = Memory(width=regwid, depth=depth, init=range(0, depth))
+        self.rdport = self.mem.read_port()
+        self.wrport = self.mem.write_port()
+
+    def elaborate(self, platform):
+        m = Module()
+        m.submodules.rdport = self.rdport
+        m.submodules.wrport = self.wrport
+        return m