From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 5 Aug 2020 10:11:12 +0000 (+0200)
Subject: interconnect/stream: set default AsyncFIFO depth to None and add depth parameter... 
X-Git-Tag: 24jan2021_ls180~22
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=303d6cca7e4139fcc9bc7ea80634b9c78048928a;p=litex.git

interconnect/stream: set default AsyncFIFO depth to None and add depth parameter to ClockDomainCrossing.
---

diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py
index 5f5bd540..86d9c375 100644
--- a/litex/soc/interconnect/stream.py
+++ b/litex/soc/interconnect/stream.py
@@ -228,7 +228,8 @@ class SyncFIFO(_FIFOWrapper):
 
 
 class AsyncFIFO(_FIFOWrapper):
-    def __init__(self, layout, depth=4, buffered=False):
+    def __init__(self, layout, depth=None, buffered=False):
+        depth = 4 if depth is None else depth
         assert depth >= 4
         _FIFOWrapper.__init__(self,
             fifo_class = fifo.AsyncFIFOBuffered if buffered else fifo.AsyncFIFO,
@@ -238,7 +239,7 @@ class AsyncFIFO(_FIFOWrapper):
 # ClockDomainCrossing ------------------------------------------------------------------------------
 
 class ClockDomainCrossing(Module):
-    def __init__(self, layout, cd_from="sys", cd_to="sys"):
+    def __init__(self, layout, cd_from="sys", cd_to="sys", depth=None):
         self.sink   = Endpoint(layout)
         self.source = Endpoint(layout)
         # # #
@@ -246,7 +247,7 @@ class ClockDomainCrossing(Module):
         if cd_from == cd_to:
             self.comb += self.sink.connect(self.source)
         else:
-            cdc = AsyncFIFO(layout)
+            cdc = AsyncFIFO(layout, depth)
             cdc = ClockDomainsRenamer({"write": cd_from, "read": cd_to})(cdc)
             self.submodules += cdc
             self.comb += self.sink.connect(cdc.sink)