From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 10 Jun 2020 12:09:45 +0000 (+0100)
Subject: starting on alu output check
X-Git-Tag: div_pipeline~432
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=305646536e47fb879cfaed2465d0f6d1e82ab895;p=soc.git

starting on alu output check
---

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index b68e0739..e373a708 100644
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -82,3 +82,10 @@ class ALUHelpers:
         else:
             yield alu.p.data_i.full_cr.eq(0)
 
+    def get_int_o(res, alu, dec2):
+        out_reg_valid = yield pdecode2.e.write_reg.ok
+        if out_reg_valid:
+            res['o'] = yield alu.n.data_o.o.data 
+
+    def check_int_o(dut, alu, sim, dec2):
+        pass