From: SergeyDegtyar Date: Tue, 17 Sep 2019 08:53:49 +0000 (+0300) Subject: adffs test update (equiv_opt -multiclock) X-Git-Tag: working-ls180~990^2~17 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=305672170bcd6346bebbb01c843225fe0392a37d;p=yosys.git adffs test update (equiv_opt -multiclock) --- diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 38c82a36f..961e08ae9 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -1,13 +1,14 @@ read_verilog adffs.v proc -async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -multiclock -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG -select -assert-count 3 t:FDRE +select -assert-count 2 t:FDCE +select -assert-count 1 t:FDRE select -assert-count 1 t:FDRE_1 -select -assert-count 5 t:LUT2 -select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 %% t:* %D +select -assert-count 1 t:LUT1 +select -assert-count 2 t:LUT2 +select -assert-none t:BUFG t:FDCE t:FDRE t:FDRE_1 t:LUT1 t:LUT2 %% t:* %D