From: lkcl <lkcl@web>
Date: Wed, 20 Apr 2022 19:23:09 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2668
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3056e166aeba1a68b5d81557a1f2347a85961ffa;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index 2dcadbed8..9c083c570 100644
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -166,18 +166,6 @@ fact big-integer multiply (more specifically, mul-and-subtract).
 
 **DRAFT**
 
-The pseudocode for `msubed RT, RA, RB, RC`` is:
-
-    prod[0:127] = (RA) * (RB)
-    sub[0:127] = EXTZ(RC) - prod
-    RT <- sub[64:127]
-    RS <- sub[0:63] # RS is either RC or RT+VL
-
-Note that RC is not sign-extended to 64-bit.  In a Vector Loop
-it contains the top half of the previous multiply-with-subtract,
-and the current product must be subtracted from it.
-
-
 Both `madded` and `msubed` are VA-Form:
 
 |0.....5|6..10|11..15|16..20|21..25|26..31|
@@ -214,6 +202,28 @@ When `EXTRA2_MODE` is set to one, the implicit RS register is identical
 to RC extended to SVP64 numbering, including whether RC is set Scalar or
 Vector.
 
+The pseudocode for `msubed RT, RA, RB, RC`` is:
+
+    prod[0:127] = (RA) * (RB)
+    sub[0:127] = EXTZ(RC) - prod
+    RT <- sub[64:127]
+    RS <- sub[0:63] # RS is either RC or RT+VL
+
+Note that RC is not sign-extended to 64-bit.  In a Vector Loop
+it contains the top half of the previous multiply-with-subtract,
+and the current product must be subtracted from it.
+
+The pseudocode for `maddx RT, RA, RB, RC` is:
+
+    prod[0:127] = (RA) * (RB)
+    sum[0:127] = EXTZ(RC) + prod
+    RT <- sum[64:127]
+    RS <- sum[0:63] # RS is either RC or RT+VL
+
+Again RC is zero-extended (not shifted), the 128-bit product added
+to it; the lower half of the result stored in RT and the upper half
+in RS.
+
 # Appendix
 
 see [[appendix]]