From: lkcl <lkcl@web>
Date: Sat, 11 Sep 2021 17:11:26 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~152
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=305cad827a6534b29e7299bc3098c7138cfd569b;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 43af023dd..c77bd3d26 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -304,8 +304,11 @@ flow alteration would not.
 
 Also, the unconditional bit `BO[0]` is still relevant when Predication
 is applied to the Branch because in `ALL` mode all nonmasked bits have
-to be tested. Even when VLSET mode is not used, CTR
-may still be decremented by the total number of nonmasked elements.
+to be tested, and when `sz=0` skipping occurs.
+Even when VLSET mode is not used, CTR
+may still be decremented by the total number of nonmasked elements,
+acting in effect as either a popcount or cntlz depending on which
+mode bits are set.
 In short, Vectorised Branch becomes an extremely powerful tool.
 
 `VLSET` mode with Vertical-First is particularly unusual. Vertical-First