From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Tue, 25 Sep 2018 16:37:06 +0000 (+0100)
Subject: arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register
X-Git-Tag: v19.0.0.0~1703
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=30746da58f3dbcb37df6214999ad48cb7df1cc4a;p=gem5.git

arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register

This patch implements AArch64 Memory Model Feature Register 2
(from ARMv8.2)

Change-Id: I16d9acaf620fac6d1206e208bd143daec1657daf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/13066
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---

diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 78dd04330..52c42cb95 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -111,6 +111,8 @@ class ArmISA(SimObject):
     # Reserved for future expansion
     id_aa64mmfr1_el1 = Param.UInt64(0x0000000000000000,
         "AArch64 Memory Model Feature Register 1")
+    id_aa64mmfr2_el1 = Param.UInt64(0x0000000000000000,
+        "AArch64 Memory Model Feature Register 2")
 
     # Any access (read/write) to an unimplemented
     # Implementation Defined registers is not causing an Undefined Instruction.
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 6063607f0..878ff70d7 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -319,6 +319,7 @@ ISA::initID64(const ArmISAParams *p)
     miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
     miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
     miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
+    miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1;
 
     miscRegs[MISCREG_ID_DFR0_EL1] =
         (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
@@ -1002,6 +1003,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
           case MISCREG_ID_AA64ISAR1_EL1:
           case MISCREG_ID_AA64MMFR0_EL1:
           case MISCREG_ID_AA64MMFR1_EL1:
+          case MISCREG_ID_AA64MMFR2_EL1:
           case MISCREG_ID_AA64PFR0_EL1:
           case MISCREG_ID_AA64PFR1_EL1:
             // ID registers are constants.
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index bbd5347e5..07123bd7d 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -1539,7 +1539,9 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
                         return MISCREG_ID_AA64MMFR0_EL1;
                       case 1:
                         return MISCREG_ID_AA64MMFR1_EL1;
-                      case 2 ... 7:
+                      case 2:
+                        return MISCREG_ID_AA64MMFR2_EL1;
+                      case 3 ... 7:
                         return MISCREG_RAZ;
                     }
                     break;
@@ -3504,6 +3506,8 @@ ISA::initializeMiscRegMetadata()
       .allPrivileges().exceptUserMode().writes(0);
     InitReg(MISCREG_ID_AA64MMFR1_EL1)
       .allPrivileges().exceptUserMode().writes(0);
+    InitReg(MISCREG_ID_AA64MMFR2_EL1)
+      .allPrivileges().exceptUserMode().writes(0);
     InitReg(MISCREG_CCSIDR_EL1)
       .allPrivileges().exceptUserMode().writes(0);
     InitReg(MISCREG_CLIDR_EL1)
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 08d6abfac..ab3fc8f7f 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -672,10 +672,10 @@ namespace ArmISA
         MISCREG_CNTHV_CVAL_EL2,         // 602
         MISCREG_CNTHV_TVAL_EL2,         // 603
 
+        MISCREG_ID_AA64MMFR2_EL1,       // 604
         // These MISCREG_FREESLOT are available Misc Register
         // slots for future registers to be implemented.
-        MISCREG_FREESLOT_1,             // 604
-        MISCREG_FREESLOT_2,             // 605
+        MISCREG_FREESLOT_1,             // 605
 
         // NUM_PHYS_MISCREGS specifies the number of actual physical
         // registers, not considering the following pseudo-registers
@@ -1388,7 +1388,7 @@ namespace ArmISA
         "cnthv_ctl_el2",
         "cnthv_cval_el2",
         "cnthv_tval_el2",
-        "freeslot1",
+        "id_aa64mmfr2_el1",
         "freeslot2",
 
         "num_phys_regs",
diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc
index 68738cba2..67bbb1493 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -415,6 +415,7 @@ TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = {
     { "id_aa64isar1_el1", MISCREG_ID_AA64ISAR1_EL1 },
     { "id_aa64mmfr0_el1", MISCREG_ID_AA64MMFR0_EL1 },
     { "id_aa64mmfr1_el1", MISCREG_ID_AA64MMFR1_EL1 },
+    { "id_aa64mmfr2_el1", MISCREG_ID_AA64MMFR2_EL1 },
     { "ccsidr_el1", MISCREG_CCSIDR_EL1 },
     { "clidr_el1", MISCREG_CLIDR_EL1 },
     { "aidr_el1", MISCREG_AIDR_EL1 },
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index dec85ef65..e642250d8 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -750,6 +750,7 @@ msrMrs64TrapToHyp(const MiscRegIndex miscReg,
       case MISCREG_ID_AA64ISAR1_EL1:
       case MISCREG_ID_AA64MMFR0_EL1:
       case MISCREG_ID_AA64MMFR1_EL1:
+      case MISCREG_ID_AA64MMFR2_EL1:
       case MISCREG_ID_AA64AFR0_EL1:
       case MISCREG_ID_AA64AFR1_EL1:
         assert(isRead);