From: Steve Reinhardt Date: Tue, 21 Apr 2009 01:54:02 +0000 (-0700) Subject: request: rename INST_READ to INST_FETCH. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3083268d60ba28cf011eadd6d6e4f400e6686cc3;p=gem5.git request: rename INST_READ to INST_FETCH. --- diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh index 96f3a901f..dd9e23f97 100644 --- a/src/cpu/ozone/inorder_back_end.hh +++ b/src/cpu/ozone/inorder_back_end.hh @@ -211,7 +211,7 @@ InorderBackEnd::read(Addr addr, T &data, unsigned flags) memReq->cmd = Read; memReq->completionEvent = NULL; memReq->time = curTick; - memReq->flags &= ~INST_READ; + memReq->flags &= ~INST_FETCH; MemAccessResult result = dcacheInterface->access(memReq); // Ugly hack to get an event scheduled *only* if the access is @@ -252,7 +252,7 @@ InorderBackEnd::write(T data, Addr addr, unsigned flags, uint64_t *res) // memcpy(memReq->data,(uint8_t *)&data,memReq->size); memReq->completionEvent = NULL; memReq->time = curTick; - memReq->flags &= ~INST_READ; + memReq->flags &= ~INST_FETCH; MemAccessResult result = dcacheInterface->access(memReq); // Ugly hack to get an event scheduled *only* if the access is @@ -293,7 +293,7 @@ InorderBackEnd::read(MemReqPtr &req, T &data, int load_idx) req->time = curTick; assert(!req->data); req->data = new uint8_t[64]; - req->flags &= ~INST_READ; + req->flags &= ~INST_FETCH; Fault fault = cpu->read(req, data); memcpy(req->data, &data, sizeof(T)); @@ -363,7 +363,7 @@ InorderBackEnd::write(MemReqPtr &req, T &data, int store_idx) memcpy(req->data,(uint8_t *)&data,req->size); req->completionEvent = NULL; req->time = curTick; - req->flags &= ~INST_READ; + req->flags &= ~INST_FETCH; MemAccessResult result = dcacheInterface->access(req); // Ugly hack to get an event scheduled *only* if the access is diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 71d26f828..5058db0da 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -48,6 +48,7 @@ #include "cpu/static_inst.hh" #include "cpu/thread_context.hh" #include "mem/packet.hh" +#include "mem/request.hh" #include "sim/byteswap.hh" #include "sim/debug.hh" #include "sim/host.hh" @@ -280,7 +281,7 @@ BaseSimpleCPU::copy(Addr dest) memReq->dest = dest_addr; memReq->size = 64; memReq->time = curTick; - memReq->flags &= ~INST_READ; + memReq->flags &= ~INST_FETCH; dcacheInterface->access(memReq); } } @@ -346,7 +347,7 @@ BaseSimpleCPU::setupFetchRequest(Request *req) #endif Addr fetchPC = (threadPC & PCMask) + fetchOffset; - req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC); + req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, threadPC); } diff --git a/src/cpu/trace/reader/itx_reader.cc b/src/cpu/trace/reader/itx_reader.cc index f27b82ff1..e03ac6905 100644 --- a/src/cpu/trace/reader/itx_reader.cc +++ b/src/cpu/trace/reader/itx_reader.cc @@ -168,7 +168,7 @@ ITXReader::getNextReq(MemReqPtr &req) break; case ITXCode: tmp_req->cmd = Read; - tmp_req->flags |= INST_READ; + tmp_req->flags |= INST_FETCH; break; default: fatal("Unknown ITX type"); diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc index ab00b3093..b286f1e40 100644 --- a/src/cpu/trace/trace_cpu.cc +++ b/src/cpu/trace/trace_cpu.cc @@ -68,7 +68,7 @@ TraceCPU::tick() while (nextReq && curTick >= nextCycle) { assert(nextReq->thread_num < 4 && "Not enough threads"); - if (nextReq->isInstRead() && icacheInterface) { + if (nextReq->isInstFetch() && icacheInterface) { if (icacheInterface->isBlocked()) break; diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc index 365ce6727..f20a306cb 100644 --- a/src/mem/cache/prefetch/base.cc +++ b/src/mem/cache/prefetch/base.cc @@ -170,7 +170,7 @@ BasePrefetcher::getPacket() Tick BasePrefetcher::notify(PacketPtr &pkt, Tick time) { - if (!pkt->req->isUncacheable() && !(pkt->req->isInstRead() && onlyData)) { + if (!pkt->req->isUncacheable() && !(pkt->req->isInstFetch() && onlyData)) { // Calculate the blk address Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1); diff --git a/src/mem/request.hh b/src/mem/request.hh index 965e58b3b..5fa682f2b 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -86,8 +86,8 @@ class Request : public FastAlloc static const FlagsType EVICT_NEXT = 0x00020000; /** The request should ignore unaligned access faults */ static const FlagsType NO_ALIGN_FAULT = 0x00040000; - /** The request was an instruction read. */ - static const FlagsType INST_READ = 0x00080000; + /** The request was an instruction fetch. */ + static const FlagsType INST_FETCH = 0x00080000; /** This request is for a memory swap. */ static const FlagsType MEM_SWAP = 0x00100000; static const FlagsType MEM_SWAP_COND = 0x00200000; @@ -98,7 +98,7 @@ class Request : public FastAlloc /** These flags are *not* cleared when a Request object is reused (assigned a new address). */ - static const FlagsType STICKY_FLAGS = INST_READ; + static const FlagsType STICKY_FLAGS = INST_FETCH; private: typedef uint8_t PrivateFlagsType; @@ -430,7 +430,7 @@ class Request : public FastAlloc /** Accessor Function to Check Cacheability. */ bool isUncacheable() const { return flags.isSet(UNCACHEABLE); } - bool isInstRead() const { return flags.isSet(INST_READ); } + bool isInstFetch() const { return flags.isSet(INST_FETCH); } bool isLLSC() const { return flags.isSet(LLSC); } bool isLocked() const { return flags.isSet(LOCKED); } bool isSwap() const { return flags.isSet(MEM_SWAP|MEM_SWAP_COND); }