From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 2 Nov 2016 19:09:57 +0000 (+0100)
Subject: Bugfix in "hierarchy -check"
X-Git-Tag: yosys-0.7~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=308a4b4a1bf39576fa87ddd8b534bf24769bb7b8;p=yosys.git

Bugfix in "hierarchy -check"
---

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 9db407c7a..e21a7a4e3 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -213,7 +213,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 					log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a port named '%s'.\n",
 							log_id(cell->type), log_id(module), log_id(cell), log_id(conn.first));
 			for (auto &param : cell->parameters)
-				if (mod->avail_parameters.count(param.first) == 0)
+				if (mod->avail_parameters.count(param.first) == 0 && param.first[0] != '$')
 					log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a parameter named '%s'.\n",
 							log_id(cell->type), log_id(module), log_id(cell), log_id(param.first));
 		}