From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 4 May 2021 17:09:54 +0000 (+0100)
Subject: add more ALUHelper routines for fast3
X-Git-Tag: 0.0.3~87
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=308b15500102f80c32205ad54f456ac3df609064;p=openpower-isa.git

add more ALUHelper routines for fast3
---

diff --git a/src/openpower/test/common.py b/src/openpower/test/common.py
index 754505ec..2ab1fe02 100644
--- a/src/openpower/test/common.py
+++ b/src/openpower/test/common.py
@@ -346,6 +346,11 @@ class ALUHelpers:
         if spr2_valid:
             res['fast2'] = yield alu.n.data_o.fast2.data
 
+    def get_fast_spr3(res, alu, dec2):
+        spr3_valid = yield alu.n.data_o.fast3.ok
+        if spr3_valid:
+            res['fast3'] = yield alu.n.data_o.fast3.data
+
     def get_cia(res, alu, dec2):
         res['cia'] = yield alu.p.data_i.cia
 
@@ -418,6 +423,14 @@ class ALUHelpers:
             cridx = yield dec2.e.write_cr.data
             res['cr_a'] = sim.crl[cridx].get_range().value
 
+    def get_wr_fast_spr3(res, sim, dec2):
+        ok = yield dec2.e.write_fast3.ok
+        if ok:
+            spr_num = yield dec2.e.write_fast3.data
+            spr_num = fast_reg_to_spr(spr_num)
+            spr_name = spr_dict[spr_num].SPR
+            res['fast3'] = sim.spr[spr_name].value
+
     def get_wr_fast_spr2(res, sim, dec2):
         ok = yield dec2.e.write_fast2.ok
         if ok: