From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 2 Aug 2019 05:21:14 +0000 (-0700)
Subject: Run "clean -purge" on holes_module in its own design
X-Git-Tag: working-ls180~1161^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3090da2d98221435f2d702efee5fa0f5d9fedc68;p=yosys.git

Run "clean -purge" on holes_module in its own design
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index a3a753912..36a379e34 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -621,8 +621,7 @@ struct XAigerWriter
 			log_debug("boxNum = %d\n", GetSize(box_list));
 			write_h_buffer(box_list.size());
 
-			RTLIL::Module *holes_module = nullptr;
-			holes_module = module->design->addModule("$__holes__");
+			RTLIL::Module *holes_module = module->design->addModule("$__holes__");
 			log_assert(holes_module);
 
 			int port_id = 1;
@@ -719,27 +718,33 @@ struct XAigerWriter
 				Pass::call(holes_module->design, "flatten -wb");
 
 				// TODO: Should techmap/aigmap/check all lib_whitebox-es just once,
-				// instead of per write_xaiger call
+				//       instead of per write_xaiger call
 				Pass::call(holes_module->design, "techmap");
 				Pass::call(holes_module->design, "aigmap");
 				for (auto cell : holes_module->cells())
 					if (!cell->type.in("$_NOT_", "$_AND_"))
 						log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
 
-				Pass::call(holes_module->design, "clean -purge");
+				holes_module->design->selection_stack.pop_back();
+
+				// Move into a new (temporary) design so that "clean" will only
+				// operate (and run checks on) this one module
+				RTLIL::Design *holes_design = new RTLIL::Design;
+				holes_module->design->modules_.erase(holes_module->name);
+				holes_design->add(holes_module);
+				Pass::call(holes_design, "clean -purge");
 
 				std::stringstream a_buffer;
 				XAigerWriter writer(holes_module, true /* holes_mode */);
 				writer.write_aiger(a_buffer, false /*ascii_mode*/);
 
-				holes_module->design->selection_stack.pop_back();
+				delete holes_design;
 
 				f << "a";
 				std::string buffer_str = a_buffer.str();
 				int32_t buffer_size_be = to_big_endian(buffer_str.size());
 				f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
 				f.write(buffer_str.data(), buffer_str.size());
-				holes_module->design->remove(holes_module);
 
 				log_pop();
 			}