From: Luke Kenneth Casson Leighton Date: Fri, 30 Mar 2018 06:57:01 +0000 (+0100) Subject: pep8 whitespace cleanup X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3090da445b8bb88436ea15426d9130748df1bda3;p=pinmux.git pep8 whitespace cleanup --- diff --git a/src/spec/interfaces.py b/src/spec/interfaces.py index 4e6829e..cf8defa 100644 --- a/src/spec/interfaces.py +++ b/src/spec/interfaces.py @@ -56,7 +56,7 @@ class Pinouts(object): i2spins = ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+'] # for i in range(4): # i2spins.append("DO%d+" % i) - pins = Pins( 'IIS', i2spins, self.bankspec, + pins = Pins('IIS', i2spins, self.bankspec, suffix, offs, bank, mux, spec, limit, origsuffix=suffix) self.pinmerge(pins) @@ -65,7 +65,7 @@ class Pinouts(object): emmcpins = ['CMD+', 'CLK+'] for i in range(8): emmcpins.append("D%d*" % i) - pins = Pins( 'MMC', emmcpins, self.bankspec, + pins = Pins('MMC', emmcpins, self.bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) self.pinmerge(pins) @@ -76,42 +76,42 @@ class Pinouts(object): for i in range(4): sdmmcpins.append("D%d*" % i) sdmmcpins = sdmmcpins[start:limit] - pins = Pins( 'SD', sdmmcpins, self.bankspec, + pins = Pins('SD', sdmmcpins, self.bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) self.pinmerge(pins) def spi(self, suffix, offs, bank, mux=1, spec=None): spipins = ['CLK*', 'NSS*', 'MOSI*', 'MISO*'] - pins = Pins( 'SPI', spipins, self.bankspec, + pins = Pins('SPI', spipins, self.bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) self.pinmerge(pins) def quadspi(self, suffix, offs, bank, mux=1, spec=None, limit=None): spipins = ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*'] - pins = Pins( 'QSPI', spipins, self.bankspec, + pins = Pins('QSPI', spipins, self.bankspec, suffix, offs, bank, mux, spec, limit, origsuffix=suffix) self.pinmerge(pins) def i2c(self, suffix, offs, bank, mux=1, spec=None): spipins = ['SDA*', 'SCL*'] - pins = Pins( 'TWI', spipins, self.bankspec, + pins = Pins('TWI', spipins, self.bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) self.pinmerge(pins) def jtag(self, suffix, offs, bank, mux=1, spec=None): jtagpins = ['MS+', 'DI-', 'DO+', 'CK+'] - pins = Pins( 'JTAG', jtagpins, self.bankspec, + pins = Pins('JTAG', jtagpins, self.bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) self.pinmerge(pins) def uart(self, suffix, offs, bank, mux=1, spec=None): uartpins = ['TX+', 'RX-'] - pins = Pins( 'UART', uartpins, self.bankspec, + pins = Pins('UART', uartpins, self.bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) self.pinmerge(pins) @@ -120,14 +120,14 @@ class Pinouts(object): ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+'] for i in range(8): ulpipins.append('D%d*' % i) - pins = Pins( 'ULPI', ulpipins, self.bankspec, + pins = Pins('ULPI', ulpipins, self.bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) self.pinmerge(pins) def uartfull(self, suffix, offs, bank, mux=1, spec=None): uartpins = ['TX+', 'RX-', 'CTS-', 'RTS+'] - pins = Pins( 'UARTQ', uartpins, self.bankspec, + pins = Pins('UARTQ', uartpins, self.bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) self.pinmerge(pins) @@ -136,7 +136,7 @@ class Pinouts(object): ttlpins = ['CK+', 'DE+', 'HS+', 'VS+'] for i in range(24): ttlpins.append("D%d+" % i) - pins = Pins( 'LCD', ttlpins, self.bankspec, + pins = Pins('LCD', ttlpins, self.bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) self.pinmerge(pins) @@ -151,7 +151,7 @@ class Pinouts(object): 'EMDC+', 'EMDIO*', 'ETXEN+', 'ETXCK+', 'ECRS-', 'ECOL+', 'ETXERR+'] - pins = Pins( 'RG', buspins, self.bankspec, + pins = Pins('RG', buspins, self.bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) self.pinmerge(pins) @@ -169,7 +169,7 @@ class Pinouts(object): buspins.append("BWE%d" % i) for i in range(2, 6): buspins.append("CS%d+" % i) - pins = Pins( 'FB', buspins, self.bankspec, + pins = Pins('FB', buspins, self.bankspec, suffix, offs, bank, mux, spec, limit, origsuffix=suffix) self.pinmerge(pins) @@ -178,7 +178,7 @@ class Pinouts(object): buspins = [] for i in range(8, 32): buspins.append("AD%d*" % i) - pins = Pins( 'FB', buspins, self.bankspec, + pins = Pins('FB', buspins, self.bankspec, suffix, offs, bank, mux, spec, limit, origsuffix=suffix) self.pinmerge(pins) @@ -199,7 +199,7 @@ class Pinouts(object): buspins.append("SDRBA%d+" % i) buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+', 'SDRRST+'] - pins = Pins( 'SDR', buspins, self.bankspec, + pins = Pins('SDR', buspins, self.bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) self.pinmerge(pins) @@ -210,7 +210,7 @@ class Pinouts(object): buspins.append("SDRCS%d#+" % i) for i in range(8, 32): buspins.append("SDRDQ%d*" % i) - pins = Pins( 'SDR', buspins, self.bankspec, + pins = Pins('SDR', buspins, self.bankspec, suffix, offs, bank, mux, spec, limit, origsuffix=suffix) self.pinmerge(pins) @@ -227,7 +227,7 @@ class Pinouts(object): buspins.append("MCUNRB%d+" % i) buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+', 'MCURST+'] - pins = Pins( 'MCU', buspins, self.bankspec, + pins = Pins('MCU', buspins, self.bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) self.pinmerge(pins) @@ -237,7 +237,7 @@ class Pinouts(object): gpiopins = [] for i in range(gpiooffs, gpiooffs + gpionum): gpiopins.append("%s%d*" % (bank, i)) - pins = Pins( prefix, gpiopins, self.bankspec, + pins = Pins(prefix, gpiopins, self.bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) self.pinmerge(pins) @@ -246,7 +246,7 @@ class Pinouts(object): gpiopins = [] for i in range(gpiooffs, gpiooffs + gpionum): gpiopins.append("%d*" % (i)) - pins = Pins( 'EINT', gpiopins, self.bankspec, + pins = Pins('EINT', gpiopins, self.bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) self.pinmerge(pins) @@ -255,7 +255,7 @@ class Pinouts(object): pwmpins = [] for i in range(pwmoffs, pwmoffs + pwmnum): pwmpins.append("%d+" % (i)) - pins = Pins( 'PWM', pwmpins, self.bankspec, + pins = Pins('PWM', pwmpins, self.bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) self.pinmerge(pins)