From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 29 Aug 2019 02:07:28 +0000 (-0700)
Subject: Add arrival for SB_MAC16.O
X-Git-Tag: working-ls180~1075^2^2~14
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=309684af16c763f7874beb605d0834c64975d004;p=yosys.git

Add arrival for SB_MAC16.O
---

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 116188acb..f4cc342eb 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1445,6 +1445,7 @@ module SB_MAC16 (
 	input ADDSUBTOP, ADDSUBBOT,
 	input OHOLDTOP, OHOLDBOT,
 	input CI, ACCUMCI, SIGNEXTIN,
+	`ABC_ARRIVAL_U(1984)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L587
 	output [31:0] O,
 	output CO, ACCUMCO, SIGNEXTOUT
 );