From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 18 Jul 2014 08:28:45 +0000 (+0200)
Subject: Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port
X-Git-Tag: yosys-0.4~551
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=309ae98246cf9ff115b7d95ae14991faf72a5a38;p=yosys.git

Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port
---

diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index 1e91d1601..a0c7a027f 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -266,6 +266,21 @@ struct OptReduceWorker
 				mem_wren_sigs.add(assign_map(cell->connections["\\D"]));
 		}
 
+		bool keep_expanding_mem_wren_sigs = true;
+		while (keep_expanding_mem_wren_sigs) {
+			keep_expanding_mem_wren_sigs = false;
+			for (auto &cell_it : module->cells) {
+				RTLIL::Cell *cell = cell_it.second;
+				if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->connections["\\Y"]))) {
+					if (!mem_wren_sigs.check_all(assign_map(cell->connections["\\A"])) ||
+							!mem_wren_sigs.check_all(assign_map(cell->connections["\\B"])))
+						keep_expanding_mem_wren_sigs = true;
+					mem_wren_sigs.add(assign_map(cell->connections["\\A"]));
+					mem_wren_sigs.add(assign_map(cell->connections["\\B"]));
+				}
+			}
+		}
+
 		while (did_something)
 		{
 			did_something = false;