From: Andrew Waterman Date: Tue, 26 Mar 2013 05:38:32 +0000 (-0700) Subject: truncate effective addresses in rv32 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=30a89f79b31b101b3ce4481e502e2e7d2529746c;p=riscv-isa-sim.git truncate effective addresses in rv32 also, employ a more efficient instruction dispatch based upon rv32 mode. --- diff --git a/.gitignore b/.gitignore index 54ac075..adc99bf 100644 --- a/.gitignore +++ b/.gitignore @@ -1,10 +1,3 @@ -#========================================================================= -# Git Ignore Files -#========================================================================= -# We explicitly ignore a default build directory and the autoconf -# generated autom4te.cache directory. This makes it easy to do a clean -# build under the source directory and still have it appear clean to git. - build/ autom4te.cache/ - +riscv/dispatch.h diff --git a/riscv/decode.h b/riscv/decode.h index fd3b292..b8a036b 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -124,7 +124,6 @@ union insn_t uint32_t bits; }; -#include template class write_port_t { @@ -184,6 +183,8 @@ private: #define TARGET insn.jtype.target #define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS)) #define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS)) +#define ITYPE_EADDR sext_xprlen(RS1 + SIMM) +#define BTYPE_EADDR sext_xprlen(RS1 + BIMM) #define RM ({ int rm = insn.ftype.rm; \ if(rm == 7) rm = (fsr & FSR_RD) >> FSR_RD_SHIFT; \ if(rm > 4) throw_illegal_instruction; \ diff --git a/riscv/dispatch b/riscv/dispatch index b96b364..231853c 100755 --- a/riscv/dispatch +++ b/riscv/dispatch @@ -1,4 +1,4 @@ -#!/usr/bin/python +#!/usr/bin/env python import sys if len(sys.argv) == 3: @@ -38,40 +38,46 @@ for i in range(0, tablesz): if filenum == numfiles: print '#include "processor.h"' - print 'const insn_func_t processor_t::dispatch_table[DISPATCH_TABLE_SIZE] = {' - for i in range(0, tablesz): - func = i - if i in redundant: - func = redundant[i] - print ' &processor_t::insn_func_%d,' % func + print 'const insn_func_t processor_t::dispatch_table[%d] = {' % (2*tablesz) + for xl in [32, 64]: + for i in range(0, tablesz): + func = i + if i in redundant: + func = redundant[i] + print ' &processor_t::insn_func_%d_%d,' % (xl, func) print '};' if filenum == numfiles+1: - print 'static const size_t DISPATCH_TABLE_SIZE = %d;' % tablesz - print 'static const insn_func_t dispatch_table[DISPATCH_TABLE_SIZE];' + print '#define get_insn_func(insn, sr) \\' + print ' processor_t::dispatch_table[((((sr) & SR_S) ? (sr & SR_S64) : (SR_U64)) ? %d : 0) + ((insn).bits %% %d)]' % (tablesz, tablesz) + + print 'static const insn_func_t dispatch_table[%d];' % (2*tablesz) for i in range(0, tablesz): if i not in redundant: - print 'reg_t insn_func_%d(insn_t insn, reg_t reg);' % i + print 'reg_t insn_func_32_%d(insn_t insn, reg_t reg);' % i + print 'reg_t insn_func_64_%d(insn_t insn, reg_t reg);' % i sys.exit(0) print '#include "insn_header.h"' for i in range(0, tablesz): - if i % numfiles != filenum or i in redundant: - continue + for xl in [32, 64]: + if i % numfiles != filenum or i in redundant: + continue - print 'reg_t processor_t::insn_func_%d(insn_t insn, reg_t pc)' % i - print '{' - for name in match.iterkeys(): - if match[name] % tablesz == (i & mask[name]): - print ' if((insn.bits & 0x%x) == 0x%x)' % (mask[name] & ~(tablesz-1), \ - match[name] & ~(tablesz-1)) - print ' {' - print ' reg_t npc = pc + insn_length(0x%x);' % match[name] - print ' #include "insns/%s.h"' % name - print ' return npc;' - print ' }' - print ' else', + print 'reg_t processor_t::insn_func_%d_%d(insn_t insn, reg_t pc)' % (xl, i) + print '{' + for name in match.iterkeys(): + if match[name] % tablesz == (i & mask[name]): + print ' if((insn.bits & 0x%x) == 0x%x)' % (mask[name] & ~(tablesz-1), \ + match[name] & ~(tablesz-1)) + print ' {' + print ' int xprlen = %d;' % xl + print ' reg_t npc = sext_xprlen(pc + insn_length(0x%x));' % match[name] + print ' #include "insns/%s.h"' % name + print ' return npc;' + print ' }' + print ' else', - print ' throw trap_illegal_instruction;' - print '}\n' + print ' throw trap_illegal_instruction;' + print '}\n' diff --git a/riscv/dispatch.h b/riscv/dispatch.h deleted file mode 100644 index a951be6..0000000 --- a/riscv/dispatch.h +++ /dev/null @@ -1,256 +0,0 @@ -static const size_t DISPATCH_TABLE_SIZE = 1024; -static const insn_func_t dispatch_table[DISPATCH_TABLE_SIZE]; -reg_t insn_func_0(insn_t insn, reg_t reg); -reg_t insn_func_1(insn_t insn, reg_t reg); -reg_t insn_func_2(insn_t insn, reg_t reg); -reg_t insn_func_3(insn_t insn, reg_t reg); -reg_t insn_func_4(insn_t insn, reg_t reg); -reg_t insn_func_5(insn_t insn, reg_t reg); -reg_t insn_func_6(insn_t insn, reg_t reg); -reg_t insn_func_7(insn_t insn, reg_t reg); -reg_t insn_func_8(insn_t insn, reg_t reg); -reg_t insn_func_9(insn_t insn, reg_t reg); -reg_t insn_func_10(insn_t insn, reg_t reg); -reg_t insn_func_11(insn_t insn, reg_t reg); -reg_t insn_func_12(insn_t insn, reg_t reg); -reg_t insn_func_13(insn_t insn, reg_t reg); -reg_t insn_func_15(insn_t insn, reg_t reg); -reg_t insn_func_16(insn_t insn, reg_t reg); -reg_t insn_func_17(insn_t insn, reg_t reg); -reg_t insn_func_18(insn_t insn, reg_t reg); -reg_t insn_func_19(insn_t insn, reg_t reg); -reg_t insn_func_20(insn_t insn, reg_t reg); -reg_t insn_func_21(insn_t insn, reg_t reg); -reg_t insn_func_22(insn_t insn, reg_t reg); -reg_t insn_func_24(insn_t insn, reg_t reg); -reg_t insn_func_25(insn_t insn, reg_t reg); -reg_t insn_func_26(insn_t insn, reg_t reg); -reg_t insn_func_27(insn_t insn, reg_t reg); -reg_t insn_func_28(insn_t insn, reg_t reg); -reg_t insn_func_29(insn_t insn, reg_t reg); -reg_t insn_func_34(insn_t insn, reg_t reg); -reg_t insn_func_35(insn_t insn, reg_t reg); -reg_t insn_func_50(insn_t insn, reg_t reg); -reg_t insn_func_51(insn_t insn, reg_t reg); -reg_t insn_func_55(insn_t insn, reg_t reg); -reg_t insn_func_57(insn_t insn, reg_t reg); -reg_t insn_func_58(insn_t insn, reg_t reg); -reg_t insn_func_59(insn_t insn, reg_t reg); -reg_t insn_func_66(insn_t insn, reg_t reg); -reg_t insn_func_67(insn_t insn, reg_t reg); -reg_t insn_func_71(insn_t insn, reg_t reg); -reg_t insn_func_75(insn_t insn, reg_t reg); -reg_t insn_func_79(insn_t insn, reg_t reg); -reg_t insn_func_82(insn_t insn, reg_t reg); -reg_t insn_func_83(insn_t insn, reg_t reg); -reg_t insn_func_89(insn_t insn, reg_t reg); -reg_t insn_func_90(insn_t insn, reg_t reg); -reg_t insn_func_98(insn_t insn, reg_t reg); -reg_t insn_func_99(insn_t insn, reg_t reg); -reg_t insn_func_103(insn_t insn, reg_t reg); -reg_t insn_func_107(insn_t insn, reg_t reg); -reg_t insn_func_111(insn_t insn, reg_t reg); -reg_t insn_func_114(insn_t insn, reg_t reg); -reg_t insn_func_115(insn_t insn, reg_t reg); -reg_t insn_func_119(insn_t insn, reg_t reg); -reg_t insn_func_121(insn_t insn, reg_t reg); -reg_t insn_func_122(insn_t insn, reg_t reg); -reg_t insn_func_123(insn_t insn, reg_t reg); -reg_t insn_func_130(insn_t insn, reg_t reg); -reg_t insn_func_131(insn_t insn, reg_t reg); -reg_t insn_func_139(insn_t insn, reg_t reg); -reg_t insn_func_143(insn_t insn, reg_t reg); -reg_t insn_func_146(insn_t insn, reg_t reg); -reg_t insn_func_147(insn_t insn, reg_t reg); -reg_t insn_func_153(insn_t insn, reg_t reg); -reg_t insn_func_154(insn_t insn, reg_t reg); -reg_t insn_func_155(insn_t insn, reg_t reg); -reg_t insn_func_162(insn_t insn, reg_t reg); -reg_t insn_func_163(insn_t insn, reg_t reg); -reg_t insn_func_175(insn_t insn, reg_t reg); -reg_t insn_func_178(insn_t insn, reg_t reg); -reg_t insn_func_179(insn_t insn, reg_t reg); -reg_t insn_func_185(insn_t insn, reg_t reg); -reg_t insn_func_186(insn_t insn, reg_t reg); -reg_t insn_func_187(insn_t insn, reg_t reg); -reg_t insn_func_194(insn_t insn, reg_t reg); -reg_t insn_func_195(insn_t insn, reg_t reg); -reg_t insn_func_199(insn_t insn, reg_t reg); -reg_t insn_func_203(insn_t insn, reg_t reg); -reg_t insn_func_207(insn_t insn, reg_t reg); -reg_t insn_func_210(insn_t insn, reg_t reg); -reg_t insn_func_211(insn_t insn, reg_t reg); -reg_t insn_func_217(insn_t insn, reg_t reg); -reg_t insn_func_218(insn_t insn, reg_t reg); -reg_t insn_func_226(insn_t insn, reg_t reg); -reg_t insn_func_227(insn_t insn, reg_t reg); -reg_t insn_func_235(insn_t insn, reg_t reg); -reg_t insn_func_242(insn_t insn, reg_t reg); -reg_t insn_func_243(insn_t insn, reg_t reg); -reg_t insn_func_247(insn_t insn, reg_t reg); -reg_t insn_func_249(insn_t insn, reg_t reg); -reg_t insn_func_250(insn_t insn, reg_t reg); -reg_t insn_func_251(insn_t insn, reg_t reg); -reg_t insn_func_258(insn_t insn, reg_t reg); -reg_t insn_func_259(insn_t insn, reg_t reg); -reg_t insn_func_263(insn_t insn, reg_t reg); -reg_t insn_func_267(insn_t insn, reg_t reg); -reg_t insn_func_271(insn_t insn, reg_t reg); -reg_t insn_func_274(insn_t insn, reg_t reg); -reg_t insn_func_275(insn_t insn, reg_t reg); -reg_t insn_func_281(insn_t insn, reg_t reg); -reg_t insn_func_282(insn_t insn, reg_t reg); -reg_t insn_func_284(insn_t insn, reg_t reg); -reg_t insn_func_290(insn_t insn, reg_t reg); -reg_t insn_func_291(insn_t insn, reg_t reg); -reg_t insn_func_295(insn_t insn, reg_t reg); -reg_t insn_func_299(insn_t insn, reg_t reg); -reg_t insn_func_303(insn_t insn, reg_t reg); -reg_t insn_func_306(insn_t insn, reg_t reg); -reg_t insn_func_307(insn_t insn, reg_t reg); -reg_t insn_func_313(insn_t insn, reg_t reg); -reg_t insn_func_314(insn_t insn, reg_t reg); -reg_t insn_func_322(insn_t insn, reg_t reg); -reg_t insn_func_338(insn_t insn, reg_t reg); -reg_t insn_func_345(insn_t insn, reg_t reg); -reg_t insn_func_346(insn_t insn, reg_t reg); -reg_t insn_func_354(insn_t insn, reg_t reg); -reg_t insn_func_363(insn_t insn, reg_t reg); -reg_t insn_func_370(insn_t insn, reg_t reg); -reg_t insn_func_371(insn_t insn, reg_t reg); -reg_t insn_func_375(insn_t insn, reg_t reg); -reg_t insn_func_377(insn_t insn, reg_t reg); -reg_t insn_func_378(insn_t insn, reg_t reg); -reg_t insn_func_379(insn_t insn, reg_t reg); -reg_t insn_func_386(insn_t insn, reg_t reg); -reg_t insn_func_387(insn_t insn, reg_t reg); -reg_t insn_func_391(insn_t insn, reg_t reg); -reg_t insn_func_395(insn_t insn, reg_t reg); -reg_t insn_func_399(insn_t insn, reg_t reg); -reg_t insn_func_402(insn_t insn, reg_t reg); -reg_t insn_func_403(insn_t insn, reg_t reg); -reg_t insn_func_409(insn_t insn, reg_t reg); -reg_t insn_func_410(insn_t insn, reg_t reg); -reg_t insn_func_418(insn_t insn, reg_t reg); -reg_t insn_func_419(insn_t insn, reg_t reg); -reg_t insn_func_423(insn_t insn, reg_t reg); -reg_t insn_func_427(insn_t insn, reg_t reg); -reg_t insn_func_434(insn_t insn, reg_t reg); -reg_t insn_func_435(insn_t insn, reg_t reg); -reg_t insn_func_441(insn_t insn, reg_t reg); -reg_t insn_func_442(insn_t insn, reg_t reg); -reg_t insn_func_450(insn_t insn, reg_t reg); -reg_t insn_func_466(insn_t insn, reg_t reg); -reg_t insn_func_473(insn_t insn, reg_t reg); -reg_t insn_func_474(insn_t insn, reg_t reg); -reg_t insn_func_482(insn_t insn, reg_t reg); -reg_t insn_func_498(insn_t insn, reg_t reg); -reg_t insn_func_499(insn_t insn, reg_t reg); -reg_t insn_func_503(insn_t insn, reg_t reg); -reg_t insn_func_505(insn_t insn, reg_t reg); -reg_t insn_func_506(insn_t insn, reg_t reg); -reg_t insn_func_507(insn_t insn, reg_t reg); -reg_t insn_func_514(insn_t insn, reg_t reg); -reg_t insn_func_515(insn_t insn, reg_t reg); -reg_t insn_func_523(insn_t insn, reg_t reg); -reg_t insn_func_530(insn_t insn, reg_t reg); -reg_t insn_func_531(insn_t insn, reg_t reg); -reg_t insn_func_537(insn_t insn, reg_t reg); -reg_t insn_func_538(insn_t insn, reg_t reg); -reg_t insn_func_540(insn_t insn, reg_t reg); -reg_t insn_func_546(insn_t insn, reg_t reg); -reg_t insn_func_559(insn_t insn, reg_t reg); -reg_t insn_func_562(insn_t insn, reg_t reg); -reg_t insn_func_563(insn_t insn, reg_t reg); -reg_t insn_func_569(insn_t insn, reg_t reg); -reg_t insn_func_570(insn_t insn, reg_t reg); -reg_t insn_func_571(insn_t insn, reg_t reg); -reg_t insn_func_578(insn_t insn, reg_t reg); -reg_t insn_func_594(insn_t insn, reg_t reg); -reg_t insn_func_595(insn_t insn, reg_t reg); -reg_t insn_func_601(insn_t insn, reg_t reg); -reg_t insn_func_602(insn_t insn, reg_t reg); -reg_t insn_func_610(insn_t insn, reg_t reg); -reg_t insn_func_611(insn_t insn, reg_t reg); -reg_t insn_func_619(insn_t insn, reg_t reg); -reg_t insn_func_626(insn_t insn, reg_t reg); -reg_t insn_func_627(insn_t insn, reg_t reg); -reg_t insn_func_631(insn_t insn, reg_t reg); -reg_t insn_func_633(insn_t insn, reg_t reg); -reg_t insn_func_634(insn_t insn, reg_t reg); -reg_t insn_func_635(insn_t insn, reg_t reg); -reg_t insn_func_642(insn_t insn, reg_t reg); -reg_t insn_func_643(insn_t insn, reg_t reg); -reg_t insn_func_651(insn_t insn, reg_t reg); -reg_t insn_func_658(insn_t insn, reg_t reg); -reg_t insn_func_659(insn_t insn, reg_t reg); -reg_t insn_func_665(insn_t insn, reg_t reg); -reg_t insn_func_666(insn_t insn, reg_t reg); -reg_t insn_func_667(insn_t insn, reg_t reg); -reg_t insn_func_674(insn_t insn, reg_t reg); -reg_t insn_func_687(insn_t insn, reg_t reg); -reg_t insn_func_690(insn_t insn, reg_t reg); -reg_t insn_func_691(insn_t insn, reg_t reg); -reg_t insn_func_697(insn_t insn, reg_t reg); -reg_t insn_func_698(insn_t insn, reg_t reg); -reg_t insn_func_699(insn_t insn, reg_t reg); -reg_t insn_func_706(insn_t insn, reg_t reg); -reg_t insn_func_722(insn_t insn, reg_t reg); -reg_t insn_func_723(insn_t insn, reg_t reg); -reg_t insn_func_729(insn_t insn, reg_t reg); -reg_t insn_func_730(insn_t insn, reg_t reg); -reg_t insn_func_738(insn_t insn, reg_t reg); -reg_t insn_func_739(insn_t insn, reg_t reg); -reg_t insn_func_754(insn_t insn, reg_t reg); -reg_t insn_func_755(insn_t insn, reg_t reg); -reg_t insn_func_759(insn_t insn, reg_t reg); -reg_t insn_func_761(insn_t insn, reg_t reg); -reg_t insn_func_762(insn_t insn, reg_t reg); -reg_t insn_func_763(insn_t insn, reg_t reg); -reg_t insn_func_770(insn_t insn, reg_t reg); -reg_t insn_func_771(insn_t insn, reg_t reg); -reg_t insn_func_779(insn_t insn, reg_t reg); -reg_t insn_func_786(insn_t insn, reg_t reg); -reg_t insn_func_787(insn_t insn, reg_t reg); -reg_t insn_func_793(insn_t insn, reg_t reg); -reg_t insn_func_794(insn_t insn, reg_t reg); -reg_t insn_func_796(insn_t insn, reg_t reg); -reg_t insn_func_802(insn_t insn, reg_t reg); -reg_t insn_func_815(insn_t insn, reg_t reg); -reg_t insn_func_818(insn_t insn, reg_t reg); -reg_t insn_func_819(insn_t insn, reg_t reg); -reg_t insn_func_825(insn_t insn, reg_t reg); -reg_t insn_func_826(insn_t insn, reg_t reg); -reg_t insn_func_827(insn_t insn, reg_t reg); -reg_t insn_func_834(insn_t insn, reg_t reg); -reg_t insn_func_850(insn_t insn, reg_t reg); -reg_t insn_func_857(insn_t insn, reg_t reg); -reg_t insn_func_858(insn_t insn, reg_t reg); -reg_t insn_func_866(insn_t insn, reg_t reg); -reg_t insn_func_867(insn_t insn, reg_t reg); -reg_t insn_func_882(insn_t insn, reg_t reg); -reg_t insn_func_889(insn_t insn, reg_t reg); -reg_t insn_func_890(insn_t insn, reg_t reg); -reg_t insn_func_891(insn_t insn, reg_t reg); -reg_t insn_func_898(insn_t insn, reg_t reg); -reg_t insn_func_914(insn_t insn, reg_t reg); -reg_t insn_func_915(insn_t insn, reg_t reg); -reg_t insn_func_921(insn_t insn, reg_t reg); -reg_t insn_func_922(insn_t insn, reg_t reg); -reg_t insn_func_930(insn_t insn, reg_t reg); -reg_t insn_func_943(insn_t insn, reg_t reg); -reg_t insn_func_946(insn_t insn, reg_t reg); -reg_t insn_func_947(insn_t insn, reg_t reg); -reg_t insn_func_953(insn_t insn, reg_t reg); -reg_t insn_func_954(insn_t insn, reg_t reg); -reg_t insn_func_955(insn_t insn, reg_t reg); -reg_t insn_func_962(insn_t insn, reg_t reg); -reg_t insn_func_978(insn_t insn, reg_t reg); -reg_t insn_func_985(insn_t insn, reg_t reg); -reg_t insn_func_986(insn_t insn, reg_t reg); -reg_t insn_func_994(insn_t insn, reg_t reg); -reg_t insn_func_995(insn_t insn, reg_t reg); -reg_t insn_func_1010(insn_t insn, reg_t reg); -reg_t insn_func_1011(insn_t insn, reg_t reg); -reg_t insn_func_1017(insn_t insn, reg_t reg); -reg_t insn_func_1018(insn_t insn, reg_t reg); diff --git a/riscv/insns/fld.h b/riscv/insns/fld.h index 123dea4..bc8b9c7 100644 --- a/riscv/insns/fld.h +++ b/riscv/insns/fld.h @@ -1,2 +1,2 @@ require_fp; -FRD = mmu.load_int64(RS1+SIMM); +FRD = mmu.load_int64(ITYPE_EADDR); diff --git a/riscv/insns/flw.h b/riscv/insns/flw.h index 335fd7d..74374b9 100644 --- a/riscv/insns/flw.h +++ b/riscv/insns/flw.h @@ -1,2 +1,2 @@ require_fp; -FRD = mmu.load_int32(RS1+SIMM); +FRD = mmu.load_int32(ITYPE_EADDR); diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h index 113398e..95fbd26 100644 --- a/riscv/insns/fsd.h +++ b/riscv/insns/fsd.h @@ -1,2 +1,2 @@ require_fp; -mmu.store_uint64(RS1+BIMM, FRS2); +mmu.store_uint64(BTYPE_EADDR, FRS2); diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h index 23d3333..59d9066 100644 --- a/riscv/insns/fsw.h +++ b/riscv/insns/fsw.h @@ -1,2 +1,2 @@ require_fp; -mmu.store_uint32(RS1+BIMM, FRS2); +mmu.store_uint32(BTYPE_EADDR, FRS2); diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h index 81ba7de..c88ee2d 100644 --- a/riscv/insns/lb.h +++ b/riscv/insns/lb.h @@ -1 +1 @@ -RD = mmu.load_int8(RS1+SIMM); +RD = mmu.load_int8(ITYPE_EADDR); diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h index 12c688a..bcef96b 100644 --- a/riscv/insns/lbu.h +++ b/riscv/insns/lbu.h @@ -1 +1 @@ -RD = mmu.load_uint8(RS1+SIMM); +RD = mmu.load_uint8(ITYPE_EADDR); diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h index 940d348..2bbe5c3 100644 --- a/riscv/insns/ld.h +++ b/riscv/insns/ld.h @@ -1,2 +1,2 @@ require_xpr64; -RD = mmu.load_int64(RS1+SIMM); +RD = mmu.load_int64(ITYPE_EADDR); diff --git a/riscv/insns/lh.h b/riscv/insns/lh.h index ec25bc4..c04302c 100644 --- a/riscv/insns/lh.h +++ b/riscv/insns/lh.h @@ -1 +1 @@ -RD = mmu.load_int16(RS1+SIMM); +RD = mmu.load_int16(ITYPE_EADDR); diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h index 0999c00..99d0985 100644 --- a/riscv/insns/lhu.h +++ b/riscv/insns/lhu.h @@ -1 +1 @@ -RD = mmu.load_uint16(RS1+SIMM); +RD = mmu.load_uint16(ITYPE_EADDR); diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h index 769c9fd..639d0e7 100644 --- a/riscv/insns/lw.h +++ b/riscv/insns/lw.h @@ -1 +1 @@ -RD = mmu.load_int32(RS1+SIMM); +RD = mmu.load_int32(ITYPE_EADDR); diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h index f8f9841..b3ebc0c 100644 --- a/riscv/insns/lwu.h +++ b/riscv/insns/lwu.h @@ -1,2 +1,2 @@ require_xpr64; -RD = mmu.load_uint32(RS1+SIMM); +RD = mmu.load_uint32(ITYPE_EADDR); diff --git a/riscv/insns/sb.h b/riscv/insns/sb.h index af5bd10..54176c0 100644 --- a/riscv/insns/sb.h +++ b/riscv/insns/sb.h @@ -1 +1 @@ -mmu.store_uint8(RS1+BIMM, RS2); +mmu.store_uint8(BTYPE_EADDR, RS2); diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h index 2009149..558428e 100644 --- a/riscv/insns/sd.h +++ b/riscv/insns/sd.h @@ -1,2 +1,2 @@ require_xpr64; -mmu.store_uint64(RS1+BIMM, RS2); +mmu.store_uint64(BTYPE_EADDR, RS2); diff --git a/riscv/insns/sh.h b/riscv/insns/sh.h index a484e1e..235e50e 100644 --- a/riscv/insns/sh.h +++ b/riscv/insns/sh.h @@ -1 +1 @@ -mmu.store_uint16(RS1+BIMM, RS2); +mmu.store_uint16(BTYPE_EADDR, RS2); diff --git a/riscv/insns/sw.h b/riscv/insns/sw.h index dbe260f..008d8c0 100644 --- a/riscv/insns/sw.h +++ b/riscv/insns/sw.h @@ -1 +1 @@ -mmu.store_uint32(RS1+BIMM, RS2); +mmu.store_uint32(BTYPE_EADDR, RS2); diff --git a/riscv/insns/vf.h b/riscv/insns/vf.h index 270c6fd..162cbe6 100644 --- a/riscv/insns/vf.h +++ b/riscv/insns/vf.h @@ -1,7 +1,7 @@ require_vector; for (int i=0; ipc = RS1+SIMM; + uts[i]->pc = ITYPE_EADDR; uts[i]->utmode = true; uts[i]->run = true; while (uts[i]->utmode) diff --git a/riscv/interactive.cc b/riscv/interactive.cc index 5b4439b..58a9066 100644 --- a/riscv/interactive.cc +++ b/riscv/interactive.cc @@ -173,7 +173,7 @@ reg_t sim_t::get_mem(const std::vector& args) int p = atoi(args[0].c_str()); if(p >= (int)num_cores()) throw trap_illegal_instruction; - mmu->set_vm_enabled(!!(procs[p]->sr & SR_VM)); + mmu->set_sr(procs[p]->sr); mmu->set_ptbr(procs[p]->mmu.get_ptbr()); addr_str = args[1]; } diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 84c9459..9f433b5 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -4,7 +4,7 @@ mmu_t::mmu_t(char* _mem, size_t _memsz) : mem(_mem), memsz(_memsz), badvaddr(0), - ptbr(0), supervisor(true), vm_enabled(false) + ptbr(0), sr(SR_S) { flush_tlb(); } @@ -35,7 +35,7 @@ reg_t mmu_t::refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch) reg_t pte = walk(addr); reg_t pte_perm = pte & PTE_PERM; - if(supervisor) // shift supervisor permission bits into user perm bits + if (sr & SR_S) // shift supervisor permission bits into user perm bits pte_perm = (pte_perm/(PTE_SX/PTE_UX)) & PTE_PERM; pte_perm |= pte & PTE_E; @@ -74,7 +74,7 @@ pte_t mmu_t::walk(reg_t addr) int shift = 8*sizeof(reg_t) - VA_BITS; if (((sreg_t)addr << shift >> shift) != (sreg_t)addr) ; - else if(!vm_enabled) + else if (!(sr & SR_VM)) { if(addr < memsz) pte = PTE_E | PTE_PERM | ((addr >> PGSHIFT) << PTE_PPN_SHIFT); diff --git a/riscv/mmu.h b/riscv/mmu.h index b2a48e6..58896ae 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -9,8 +9,6 @@ #include "memtracer.h" #include -class processor_t; - // virtual memory configuration typedef reg_t pte_t; const reg_t LEVELS = sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2; @@ -105,8 +103,7 @@ public: reg_t addr_lo = translate(addr, 2, false, true); insn_fetch_t fetch; fetch.insn.bits = *(uint16_t*)(mem + addr_lo); - size_t dispatch_idx = fetch.insn.bits % processor_t::DISPATCH_TABLE_SIZE; - fetch.func = processor_t::dispatch_table[dispatch_idx]; + fetch.func = get_insn_func(fetch.insn, sr); if(!INSN_IS_RVC(fetch.insn.bits)) { @@ -124,8 +121,7 @@ public: { reg_t paddr = translate(addr, sizeof(insn_t), false, true); fetch.insn = *(insn_t*)(mem + paddr); - size_t dispatch_idx = fetch.insn.bits % processor_t::DISPATCH_TABLE_SIZE; - fetch.func = processor_t::dispatch_table[dispatch_idx]; + fetch.func = get_insn_func(fetch.insn, sr); reg_t idx = (paddr/sizeof(insn_t)) % ICACHE_ENTRIES; icache_tag[idx] = addr; @@ -150,10 +146,8 @@ public: // get/set the page table base register reg_t get_ptbr() { return ptbr; } void set_ptbr(reg_t addr) { ptbr = addr & ~(PGSIZE-1); flush_tlb(); } - // keep the MMU in sync with processor mode - void set_supervisor(bool sup) { supervisor = sup; } - void set_vm_enabled(bool en) { vm_enabled = en; } + void set_sr(uint32_t _sr) { sr = _sr; } // flush the TLB and instruction cache void flush_tlb(); @@ -166,8 +160,7 @@ private: size_t memsz; reg_t badvaddr; reg_t ptbr; - bool supervisor; - bool vm_enabled; + uint32_t sr; memtracer_list_t tracer; // implement a TLB for simulator performance diff --git a/riscv/processor.cc b/riscv/processor.cc index b90bdd6..9f87f75 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -221,8 +221,7 @@ void processor_t::set_pcr(int which, reg_t val) sr &= ~SR_EV; #endif // update MMU state and flush TLB - mmu.set_vm_enabled(sr & SR_VM); - mmu.set_supervisor(sr & SR_S); + mmu.set_sr(sr); mmu.flush_tlb(); // set the fixed-point register length xprlen = ((sr & SR_S) ? (sr & SR_S64) : (sr & SR_U64)) ? 64 : 32;