From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 5 Jul 2021 21:03:15 +0000 (+0100)
Subject: fix svremap field offsets
X-Git-Tag: xlen-bcd~342
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=30aeaf915aa24239829ff53f1ee1a14abe12d522;p=openpower-isa.git

fix svremap field offsets
---

diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text
index 542429dc..490d992f 100644
--- a/openpower/isatables/fields.text
+++ b/openpower/isatables/fields.text
@@ -276,8 +276,8 @@
    | PO   |   RS  |   RA | RC  | SVDS |  XO    |
 
 # 1.6.33 SVM-FORM
-   |0     |6        |11      |16     |21    |31  |
-   | PO   |  SVxd   |   SXyd |  SVRM |   XO |  / |
+   |0     |6        |11      |16    |21    |26    |31  |
+   | PO   |  SVxd   |   SVyd | SVzd | SVRM |   XO |  / |
 
 # 1.6.28 Instruction Fields
     A (6)
diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 1ee2b51a..d769031e 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -398,6 +398,8 @@ def get_pdecode_idx_in(dec2, name):
                                      in3, in3_isvec)
     log ("get_pdecode_idx_in FRS in3", name, in3_sel, In3Sel.FRS.value,
                                      in3, in3_isvec)
+    log ("get_pdecode_idx_in FRB in2", name, in2_sel, In2Sel.FRB.value,
+                                     in2, in2_isvec)
     log ("get_pdecode_idx_in FRC in3", name, in3_sel, In3Sel.FRC.value,
                                      in3, in3_isvec)
     # identify which regnames map to in1/2/3
@@ -1200,7 +1202,7 @@ class ISACaller:
         # using pre-arranged schedule.  all of this is awful but it is a
         # start.  next job will be to put the proper activation in place
         yield self.dec2.remap_active.eq(1 if self.last_op_svshape else 0)
-        if self.last_op_svshape:
+        if self.is_svp64_mode and self.last_op_svshape:
             # get four SVSHAPEs. here we are hard-coding
             # SVSHAPE0 to FRT, SVSHAPE1 to FRA, SVSHAPE2 to FRC and
             # SVSHAPE3 to FRB, assuming "fmadd FRT, FRA, FRC, FRB."
@@ -1208,10 +1210,14 @@ class ISACaller:
             SVSHAPE1 = self.spr['SVSHAPE1']
             SVSHAPE2 = self.spr['SVSHAPE2']
             SVSHAPE3 = self.spr['SVSHAPE3']
-            print ("svshape0", bin(SVSHAPE0.value))
-            print ("    xdim", SVSHAPE0.xdimsz)
-            print ("    ydim", SVSHAPE0.ydimsz)
-            print ("    zdim", SVSHAPE0.zdimsz)
+            for i in range(4):
+                sname = 'SVSHAPE%d' % i
+                shape = self.spr[sname]
+                print (sname, bin(shape.value))
+                print ("    lims", shape.lims)
+                print ("    mode", shape.mode)
+                print ("    skip", shape.skip)
+
             remaps = [SVSHAPE0.get_iterator(),
                       SVSHAPE1.get_iterator(),
                       SVSHAPE2.get_iterator(),
@@ -1231,9 +1237,9 @@ class ISACaller:
                 elif i == 1:
                     yield self.dec2.in1_step.eq(remap_idx)
                 elif i == 2:
-                    yield self.dec2.in2_step.eq(remap_idx)
-                elif i == 3:
                     yield self.dec2.in3_step.eq(remap_idx)
+                elif i == 3:
+                    yield self.dec2.in2_step.eq(remap_idx)
                 rremaps.append((i, idx, remap_idx))
             for x in rremaps:
                 print ("shape remap", x)
diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
index 28d42cac..926c1b30 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
@@ -34,6 +34,7 @@ class DecoderTestCase(FHDLTestCase):
         """
         lst = SVP64Asm(["svremap 2, 2, 3, 0",
                        "sv.fmadds 0.v, 8.v, 16.v, 0.v"
+                       #"fmadds 0, 0, 0, 4"
                         ])
         lst = list(lst)
 
diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index e233eb22..beef6a4d 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -202,8 +202,8 @@ class SVP64Asm:
             fields = list(map(int, fields))
             insn |= (fields[0]-1) << (31-10) # SVxd       , bits 6-10
             insn |= (fields[1]-1) << (31-15) # SVyd       , bits 11-15
-            insn |= (fields[2]-1) << (31-16) # SVzd       , bits 16-20
-            insn |= (fields[3]) << (31-21) # SVRM       , bits 21-25
+            insn |= (fields[2]-1) << (31-20) # SVzd       , bits 16-20
+            insn |= (fields[3])   << (31-25) # SVRM       , bits 21-25
             insn |= 0b00001   << (31-30) # XO       , bits 26..30
             log ("svremap", bin(insn))
             yield ".long 0x%x" % insn