From: lkcl <lkcl@web>
Date: Sat, 14 May 2022 23:16:31 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2235
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=30afd151c2fe8cbb43934dbef58e32d48727610e;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn
index 0ea804a53..7eef6c125 100644
--- a/openpower/sv/biginteger/analysis.mdwn
+++ b/openpower/sv/biginteger/analysis.mdwn
@@ -161,7 +161,7 @@ to reference an alternate starting point in
 the registers containing the Vector elements
 because SVP64 sits on top of a standard Scalar register file.
 `sv.sld r16.v, r26.v, t1` for example is equivalent to shifting
-by an extra 64 bits.
+by an extra 64 bits, compared to `sv.sld r16.v, r25.v, t1`.
 
 # Vector Multiply