From: lkcl <lkcl@web>
Date: Sun, 24 Jul 2022 10:58:07 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1052
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=30c20f6a10eca7121dba0d667f95e38bb5d02d6d;p=libreriscv.git

---

diff --git a/openpower/sv/vector_isa_comparison.mdwn b/openpower/sv/vector_isa_comparison.mdwn
index 347ade40b..10a6a7a0f 100644
--- a/openpower/sv/vector_isa_comparison.mdwn
+++ b/openpower/sv/vector_isa_comparison.mdwn
@@ -96,6 +96,19 @@ It is clear that it is expected to deploy Multi-Issue to achieve
 high performance, which is a much cleaner approach that has not
 resulted in ISA poisoning such as that suffered by x86 (AVX).
 
+# Under investigation
+
+* [ETA-10](http://50.204.185.175/collections/catalog/102641713)
+  an extremely rare Scalable Vector Architecture from 1986,
+  similar to the CDC Cyber 205.
+  Only 25 machines were ever delivered. Page 3-220 of its ISA
+  shows that it had Predicate Masks and Horizontal Reduction.
+  Appendix H-1 shows it is likely a Memory-to-Memory Vector
+  Architecture, and overcame the penalties normally associated
+  with this by adding an explicit "Vector operand forwarding/chaining"
+  instruction (Page 3-69).  It is however clearly Scalable, up to Vector
+  elements of 2^16.
+
 # Actual 3D GPU Architectures and ISAs (all SIMD)
 
 All of these are not Vector ISAs, they are SIMD ISAs.
@@ -115,7 +128,6 @@ All of these are not Vector ISAs, they are SIMD ISAs.
   implement a subset of the AMDGPU ISA (Southern Islands), aka a "GPGPU"
   <https://miaowgpu.org/>
 
-
 # Actual Scalar Vector Processor Architectures and ISAs
 
 * NEC SX Aurora