From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 21 Mar 2021 13:18:30 +0000 (+0000)
Subject: adjust syntax of SVP64 predicate test cas
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=30da7b114581e5259ada027197f868f5b8b61609;p=soc.git

adjust syntax of SVP64 predicate test cas
---

diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py
index 4ae5e8ae..3b42ef4a 100644
--- a/src/soc/fu/alu/test/svp64_cases.py
+++ b/src/soc/fu/alu/test/svp64_cases.py
@@ -228,7 +228,7 @@ class SVP64ALUTestCase(TestAccumulatorBase):
         # expected results:
         # r5 = 0x0                   dest r3 is 0b10: skip
         # r6 = 0xffff_ffff_ffff_ff91 2nd bit of r3 is 1
-        isa = SVP64Asm(['svextsb/sm=~r3/m=r3 5.v, 9.v'])
+        isa = SVP64Asm(['sv.extsb/sm=~r3/m=r3 5.v, 9.v'])
         lst = list(isa)
         print("listing", lst)