From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 19 Dec 2014 16:54:44 +0000 (+0100)
Subject: Fixed another bug in write_blif handling of $lut cells
X-Git-Tag: yosys-0.5~245
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=30de490d867e4eaf9a7eb59ca85b976179b346ba;p=yosys.git

Fixed another bug in write_blif handling of $lut cells
---

diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index 366ed0369..6422d9f01 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -220,7 +220,7 @@ struct BlifDumper
 				auto &inputs = cell->getPort("\\A");
 				auto width = cell->parameters.at("\\WIDTH").as_int();
 				log_assert(inputs.size() == width);
-				for (int i = 0; i < inputs.size(); i++) {
+				for (int i = width-1; i >= 0; i--) {
 					f << stringf(" %s", cstr(inputs.extract(i, 1)));
 				}
 				auto &output = cell->getPort("\\Y");