From: Luke Kenneth Casson Leighton Date: Sun, 24 Jul 2022 22:18:20 +0000 (+0100) Subject: try hr in table X-Git-Tag: opf_rfc_ls005_v1~1047 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=30eeeffc6155a1310bd97844c294aaf786bdc90b;p=libreriscv.git try hr in table --- diff --git a/openpower/sv/executive_summary.mdwn b/openpower/sv/executive_summary.mdwn index 8bf6a42cf..e58258f49 100644 --- a/openpower/sv/executive_summary.mdwn +++ b/openpower/sv/executive_summary.mdwn @@ -48,15 +48,15 @@ We invented Simple-V to be simple because we don't like complicated. |---------------------------------------------------------------------------------------------| | **Unit tests and simulator for Power ISA v3.0 and SVP64** | | | -|---------------------------------------------------------------------------------------------| +| - - - | | **pypowersim tutorial** | | | -|---------------------------------------------------------------------------------------------| +| - - - | | **several thousand more ISA unit tests** | | | -|---------------------------------------------------------------------------------------------| +| - - - | | **demo, showing 4.5x reduction in program size for MP3 decode, greatly simplifies assembler development** | | | -|---------------------------------------------------------------------------------------------| +| - - - | | **binutils support for SVP64** | | |