From: Andy Hutchinson <hutchinsonandy@aim.com>
Date: Mon, 9 Jun 2008 22:38:34 +0000 (+0000)
Subject: re PR middle-end/36447 (simplify_subreg ICE with right shift more than length type... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3115c00d859324d044aa4cf0a150d9b47c3a82c9;p=gcc.git

re PR middle-end/36447 (simplify_subreg ICE with right shift more than length type AVR)

PR middle-end/36447
* simplify-rtx.c (simplify_subreg): Add check for shift count greater than size.

From-SVN: r136602
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f3fbaa29f93..de089334244 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2008-06-09  Andy Hutchinson  <hutchinsonandy@aim.com>
+
+	PR middle-end/36447
+	* simplify-rtx.c (simplify_subreg): Add check for shift count 
+	greater than size.
+
 2008-06-09  Richard Sandiford  <rdsandiford@googlemail.com>
 
 	* doc/md.texi: Synchronize with later constraints.md change.
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index 15e4c2a3424..262c9194937 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -5265,6 +5265,7 @@ simplify_subreg (enum machine_mode outermode, rtx op,
       && GET_MODE_BITSIZE (innermode) >= (2 * GET_MODE_BITSIZE (outermode))
       && GET_CODE (XEXP (op, 1)) == CONST_INT
       && (INTVAL (XEXP (op, 1)) & (GET_MODE_BITSIZE (outermode) - 1)) == 0
+      && INTVAL (XEXP (op, 1)) < GET_MODE_BITSIZE (innermode)      
       && byte == subreg_lowpart_offset (outermode, innermode))
     {
       int shifted_bytes = INTVAL (XEXP (op, 1)) / BITS_PER_UNIT;