From: Claire Xenia Wolf <claire@clairexen.net>
Date: Mon, 13 Dec 2021 17:20:08 +0000 (+0100)
Subject: Add YOSYS to the implicitly defined verilog macros in verific
X-Git-Tag: yosys-0.13~30^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=313340aed5e7d21a52d67c0a3c2bbc1623e87315;p=yosys.git

Add YOSYS to the implicitly defined verilog macros in verific

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 2c2858514..d5574f95a 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2295,7 +2295,7 @@ struct VerificPass : public Pass {
 		log("\n");
 		log("Additional -D<macro>[=<value>] options may be added after the option indicating\n");
 		log("the language version (and before file names) to set additional verilog defines.\n");
-		log("The macros SYNTHESIS and VERIFIC are defined implicitly.\n");
+		log("The macros YOSYS, SYNTHESIS, and VERIFIC are defined implicitly.\n");
 		log("\n");
 		log("\n");
 		log("    verific -formal <verilog-file>..\n");
@@ -2713,6 +2713,7 @@ struct VerificPass : public Pass {
 			else
 				log_abort();
 
+			veri_file::DefineMacro("YOSYS");
 			veri_file::DefineMacro("VERIFIC");
 			veri_file::DefineMacro(args[argidx] == "-formal" ? "FORMAL" : "SYNTHESIS");