From: Jason Ekstrand Date: Tue, 13 Jun 2017 16:29:42 +0000 (-0700) Subject: i965/blorp: Do an end-of-pipe sync around CCS ops X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=314ec7b46ffa1640c0d9448e7752c2d7f6c18734;p=mesa.git i965/blorp: Do an end-of-pipe sync around CCS ops Cc: "17.1" Reviewed-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 355f936f068..4146f2986d2 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -827,9 +827,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb, * and again afterwards to ensure that the resolve is complete before we * do any more regular drawing. */ - brw_emit_pipe_control_flush(brw, - PIPE_CONTROL_RENDER_TARGET_FLUSH | - PIPE_CONTROL_CS_STALL); + brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH); struct blorp_batch batch; blorp_batch_init(&brw->blorp, &batch, brw, 0); @@ -839,9 +837,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb, x0, y0, x1, y1); blorp_batch_finish(&batch); - brw_emit_pipe_control_flush(brw, - PIPE_CONTROL_RENDER_TARGET_FLUSH | - PIPE_CONTROL_CS_STALL); + brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH); /* Now that the fast clear has occurred, put the buffer in * INTEL_FAST_CLEAR_STATE_CLEAR so that we won't waste time doing @@ -936,9 +932,7 @@ brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt, * and again afterwards to ensure that the resolve is complete before we * do any more regular drawing. */ - brw_emit_pipe_control_flush(brw, - PIPE_CONTROL_RENDER_TARGET_FLUSH | - PIPE_CONTROL_CS_STALL); + brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH); struct blorp_batch batch; @@ -949,9 +943,7 @@ brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt, blorp_batch_finish(&batch); /* See comment above */ - brw_emit_pipe_control_flush(brw, - PIPE_CONTROL_RENDER_TARGET_FLUSH | - PIPE_CONTROL_CS_STALL); + brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH); } /**