From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 8 Apr 2019 09:05:40 +0000 (+0100)
Subject: clarify ascii-art
X-Git-Tag: ls180-24jan2020~1282
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3151ed061906979722138c2ddb140237e02f70e7;p=ieee754fpu.git

clarify ascii-art
---

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index 0efa4410..b3266ddd 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -782,11 +782,8 @@ class UnbufferedPipeline2(ControlBase):
         stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
         stage-1   p.o_ready <<out  stage   n.i_ready <<in    stage+1
         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
-                              |             |
-                            r_data        result
-                              |             |
-                              +--process ->-+
-
+                              |             |    |
+                              +- process-> buf <-+
         Attributes:
         -----------
         p.i_data : StageInput, shaped according to ispec