From: Shivani Parekh <shparekh@ucdavis.edu>
Date: Thu, 6 Aug 2020 00:37:15 +0000 (-0700)
Subject: systemc,sim: Update port terminology
X-Git-Tag: v20.1.0.0~221
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=315a8c2c9a3221d6872e13c9c5fd94718e77a726;p=gem5.git

systemc,sim: Update port terminology

Change-Id: Iaeafe94245e383fcb1146c99c893fd56fe9bb636
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32316
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/sim/System.py b/src/sim/System.py
index e028f48b8..dcef74be1 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -51,7 +51,7 @@ class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing',
 class System(SimObject):
     type = 'System'
     cxx_header = "sim/system.hh"
-    system_port = MasterPort("System port")
+    system_port = RequestPort("System port")
 
     cxx_exports = [
         PyBindMethod("getMemoryMode"),
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 9480821ec..8e2c47258 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -79,7 +79,7 @@ class System : public SimObject, public PCEventScope
      * master for debug access and for non-structural entities that do
      * not have a port of their own.
      */
-    class SystemPort : public MasterPort
+    class SystemPort : public RequestPort
     {
       public:
 
@@ -87,7 +87,7 @@ class System : public SimObject, public PCEventScope
          * Create a system port with a name and an owner.
          */
         SystemPort(const std::string &_name, SimObject *_owner)
-            : MasterPort(_name, _owner)
+            : RequestPort(_name, _owner)
         { }
         bool recvTimingResp(PacketPtr pkt) override
         { panic("SystemPort does not receive timing!\n"); return false; }
@@ -237,7 +237,7 @@ class System : public SimObject, public PCEventScope
      *
      * @return a reference to the system port we own
      */
-    MasterPort& getSystemPort() { return _systemPort; }
+    RequestPort& getSystemPort() { return _systemPort; }
 
     /**
      * Additional function to return the Port of a memory object.
diff --git a/src/systemc/tlm_bridge/TlmBridge.py b/src/systemc/tlm_bridge/TlmBridge.py
index 621815340..185146470 100644
--- a/src/systemc/tlm_bridge/TlmBridge.py
+++ b/src/systemc/tlm_bridge/TlmBridge.py
@@ -37,7 +37,7 @@ class Gem5ToTlmBridgeBase(SystemC_ScModule):
 
     system = Param.System(Parent.any, "system")
 
-    gem5 = SlavePort('gem5 slave port')
+    gem5 = ResponsePort('gem5 slave port')
     addr_ranges = VectorParam.AddrRange([],
             'Addresses served by this port\'s TLM side')
 
@@ -49,7 +49,7 @@ class TlmToGem5BridgeBase(SystemC_ScModule):
 
     system = Param.System(Parent.any, "system")
 
-    gem5 = MasterPort('gem5 master port')
+    gem5 = RequestPort('gem5 master port')
 
 
 class Gem5ToTlmBridge32(Gem5ToTlmBridgeBase):
diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.hh b/src/systemc/tlm_bridge/gem5_to_tlm.hh
index afc8ad905..7e69e3c64 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.hh
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.hh
@@ -85,7 +85,7 @@ template <unsigned int BITWIDTH>
 class Gem5ToTlmBridge : public Gem5ToTlmBridgeBase
 {
   private:
-    class BridgeSlavePort : public SlavePort
+    class BridgeSlavePort : public ResponsePort
     {
       protected:
         Gem5ToTlmBridge<BITWIDTH> &bridge;
@@ -130,7 +130,7 @@ class Gem5ToTlmBridge : public Gem5ToTlmBridgeBase
       public:
         BridgeSlavePort(const std::string &name_,
                         Gem5ToTlmBridge<BITWIDTH> &bridge_) :
-            SlavePort(name_, nullptr), bridge(bridge_)
+            ResponsePort(name_, nullptr), bridge(bridge_)
         {}
     };
 
diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.hh b/src/systemc/tlm_bridge/tlm_to_gem5.hh
index 03bac29b3..e2e7540f5 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.hh
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.hh
@@ -89,7 +89,7 @@ class TlmToGem5Bridge : public TlmToGem5BridgeBase
         TlmSenderState(tlm::tlm_generic_payload &trans) : trans(trans) {}
     };
 
-    class BridgeMasterPort : public MasterPort
+    class BridgeMasterPort : public RequestPort
     {
       protected:
         TlmToGem5Bridge<BITWIDTH> &bridge;
@@ -105,7 +105,7 @@ class TlmToGem5Bridge : public TlmToGem5BridgeBase
       public:
         BridgeMasterPort(const std::string &name_,
                          TlmToGem5Bridge<BITWIDTH> &bridge_) :
-            MasterPort(name_, nullptr), bridge(bridge_)
+            RequestPort(name_, nullptr), bridge(bridge_)
         {}
     };