From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 5 Apr 2019 22:37:12 +0000 (+0100)
Subject: hooray, p_o_ready works
X-Git-Tag: ls180-24jan2020~1332
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=315c14a7b537dc2b9ae6a2276fb06834c5c1325b;p=ieee754fpu.git

hooray, p_o_ready works
---

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index e32a0c67..2cb7d1ab 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -197,8 +197,12 @@ class PrevControl:
         vlen = len(self.i_valid)
         if vlen > 1: # multi-bit case: valid only when i_valid is all 1s
             all1s = Const(-1, (len(self.i_valid), False))
+            if self.stage_ctl:
+                return self.i_valid == all1s & self.s_o_ready
             return self.i_valid == all1s
         # single-bit i_valid case
+        if self.stage_ctl:
+            return self.i_valid & self.s_o_ready
         return self.i_valid
 
 
diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 7cdb7ebd..28a48db4 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -587,7 +587,7 @@ class ExampleStageDelayCls(StageCls):
     """
 
     def __init__(self):
-        self.count = Signal(3)
+        self.count = Signal(2)
 
     def ispec(self):
         return Signal(16, name="example_input_signal")
@@ -597,7 +597,6 @@ class ExampleStageDelayCls(StageCls):
 
     @property
     def p_o_ready(self):
-        return Const(1)
         return self.count == 0
 
     @property
@@ -611,7 +610,7 @@ class ExampleStageDelayCls(StageCls):
 
     def elaborate(self, platform):
         m = Module()
-        m.d.sync += self.count.eq(~self.count)
+        m.d.sync += self.count.eq(self.count + 1)
         return m