From: whitequark Date: Sun, 15 Dec 2019 11:46:14 +0000 (+0000) Subject: hdl.mem: fix src_loc_at in ReadPort, WritePort. X-Git-Tag: v0.2~43 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=318274d5a02a03ac0188bd4fa75251dd7c03e334;p=nmigen.git hdl.mem: fix src_loc_at in ReadPort, WritePort. --- diff --git a/nmigen/hdl/mem.py b/nmigen/hdl/mem.py index 93d5d16..230bfa6 100644 --- a/nmigen/hdl/mem.py +++ b/nmigen/hdl/mem.py @@ -74,9 +74,9 @@ class ReadPort(Elaboratable): self.transparent = transparent self.addr = Signal(range(memory.depth), - name="{}_r_addr".format(memory.name), src_loc_at=2 + src_loc_at) + name="{}_r_addr".format(memory.name), src_loc_at=1 + src_loc_at) self.data = Signal(memory.width, - name="{}_r_data".format(memory.name), src_loc_at=2 + src_loc_at) + name="{}_r_data".format(memory.name), src_loc_at=1 + src_loc_at) if self.domain != "comb" and not transparent: self.en = Signal(name="{}_r_en".format(memory.name), reset=1, src_loc_at=2 + src_loc_at) @@ -151,11 +151,11 @@ class WritePort(Elaboratable): self.granularity = granularity self.addr = Signal(range(memory.depth), - name="{}_w_addr".format(memory.name), src_loc_at=2 + src_loc_at) + name="{}_w_addr".format(memory.name), src_loc_at=1 + src_loc_at) self.data = Signal(memory.width, - name="{}_w_data".format(memory.name), src_loc_at=2 + src_loc_at) + name="{}_w_data".format(memory.name), src_loc_at=1 + src_loc_at) self.en = Signal(memory.width // granularity, - name="{}_w_en".format(memory.name), src_loc_at=2 + src_loc_at) + name="{}_w_en".format(memory.name), src_loc_at=1 + src_loc_at) def elaborate(self, platform): f = Instance("$memwr",