From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 12 May 2020 20:57:18 +0000 (+0100)
Subject: temporary reorg of reg/immediate reading
X-Git-Tag: div_pipeline~1268
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=318c1c3ceeab3a58f79930d49006e2bf67a42de2;p=soc.git

temporary reorg of reg/immediate reading
---

diff --git a/src/soc/alu/input_stage.py b/src/soc/alu/input_stage.py
index 37bc3317..e3511eec 100644
--- a/src/soc/alu/input_stage.py
+++ b/src/soc/alu/input_stage.py
@@ -15,7 +15,7 @@ class ALUInputStage(PipeModBase):
         super().__init__(pspec, "input")
 
     def ispec(self):
-        return ALUInputData(self.pspec) # XXX TODO, change to ALUFirstInputData
+        return ALUInputData(self.pspec)
 
     def ospec(self):
         return ALUInputData(self.pspec)
@@ -42,11 +42,11 @@ class ALUInputStage(PipeModBase):
         # remove this, just do self.o.b.eq(self.i.b) and move the
         # immediate-detection into set_alu_inputs in the unit test
         # If there's an immediate, set the B operand to that
-        with m.If(self.i.ctx.op.imm_data.imm_ok &
-                  ~(self.i.ctx.op.insn_type == InternalOp.OP_RLC)):
-            comb += self.o.b.eq(self.i.ctx.op.imm_data.imm)
-        with m.Else():
-            comb += self.o.b.eq(self.i.b)
+        comb += self.o.b.eq(self.i.b)
+
+        ##### operand C? #####
+
+        comb += self.o.c.eq(self.i.c)
 
         ##### carry-in #####
 
diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py
index a31c5fe3..61850b2c 100644
--- a/src/soc/alu/test/test_pipe_caller.py
+++ b/src/soc/alu/test/test_pipe_caller.py
@@ -40,18 +40,34 @@ def set_alu_inputs(alu, dec2, sim):
 
     reg3_ok = yield dec2.e.read_reg3.ok
     if reg3_ok:
-        reg3_sel = yield dec2.e.read_reg3.data
-        inputs.append(sim.gpr(reg3_sel).value)
+        data3 = yield dec2.e.read_reg3.data
+        data3 = sim.gpr(data3).value
+        inputs.append(data3)
+    else:
+        data3 = 0
+
     reg1_ok = yield dec2.e.read_reg1.ok
     if reg1_ok:
-        reg1_sel = yield dec2.e.read_reg1.data
-        inputs.append(sim.gpr(reg1_sel).value)
-    reg2_ok = yield dec2.e.read_reg2.ok
-    if reg2_ok:
-        reg2_sel = yield dec2.e.read_reg2.data
-        inputs.append(sim.gpr(reg2_sel).value)
+        data1 = yield dec2.e.read_reg1.data
+        data1 = sim.gpr(data1).value
+        inputs.append(data1)
+    else:
+        data1 = 0
 
-    print(inputs)
+    # If there's an immediate, set the B operand to that
+    reg2_ok = yield dec2.e.read_reg2.ok
+    imm_ok = yield dec2.e.imm_data.imm_ok
+    if imm_ok:
+        data2 = yield dec2.e.imm_data.imm
+        inputs.append(data2)
+    elif reg2_ok:
+        data2 = yield dec2.e.read_reg2.data
+        data2 = sim.gpr(data2).value
+        inputs.append(data2)
+    else:
+        data2 = 0
+
+    print("inputs", inputs)
 
     if len(inputs) == 0:
         yield alu.p.data_i.a.eq(0)
@@ -63,6 +79,7 @@ def set_alu_inputs(alu, dec2, sim):
         yield alu.p.data_i.a.eq(inputs[0])
         yield alu.p.data_i.b.eq(inputs[1])
 
+
 def set_extra_alu_inputs(alu, dec2, sim):
     carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
     yield alu.p.data_i.carry_in.eq(carry)