From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 6 Oct 2020 19:18:02 +0000 (+0100)
Subject: update comments on pimem.py
X-Git-Tag: 24jan2021_ls180~201
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=318c7c1bfe5bab47fe0f55aacb58fb81a2ee398d;p=soc.git

update comments on pimem.py
---

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index e0fadc82..09d13829 100644
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -120,18 +120,18 @@ class PortInterface(RecordObject):
         self.priv_mode     = Signal()  # privileged mode
 
         # mmu
-        self.mmu_done          = Signal()
-        self.mmu_err           = Signal()
-        self.mmu_invalid       = Signal()
+        self.mmu_done          = Signal() # keep for now
+        self.mmu_err           = Signal() # XXX remove: already in LDSTException
+        self.mmu_invalid       = Signal() # XXX remove: already in LDSTException
         # radix tree is invalid
-        self.mmu_badtree       = Signal()
+        self.mmu_badtree       = Signal() # XXX remove: already in LDSTException
         # segment_check fails
-        self.mmu_segerr        = Signal()
+        self.mmu_segerr        = Signal() # XXX remove: already in LDSTException
         # permission error takes precedence over RC error
-        self.mmu_perm_error    = Signal()
-        self.mmu_rc_error      = Signal()
+        self.mmu_perm_error    = Signal() # XXX remove: already in LDSTException
+        self.mmu_rc_error      = Signal() # XXX remove: already in LDSTException
         # r.prtbl or r.pid
-        self.mmu_sprval        = Signal(64)
+        self.mmu_sprval        = Signal(64) # XXX remove: not needed
 
         # dcache
         self.ldst_error        = Signal()