From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 7 Jul 2020 14:42:52 +0000 (+0100)
Subject: add halted condition in ISACaller, when attn instruction encountered
X-Git-Tag: div_pipeline~162^2~10
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=318d7410b3e995de9b8fc47d181e75c73df192ec;p=soc.git

add halted condition in ISACaller, when attn instruction encountered
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index fa0fb341..7d73551a 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -247,6 +247,7 @@ class ISACaller:
                        disassembly=None,
                        initial_pc=0):
 
+        self.halted = False
         self.respect_pc = respect_pc
         if initial_sprs is None:
             initial_sprs = {}
@@ -523,6 +524,10 @@ class ISACaller:
         return asmop
 
     def call(self, name):
+        if self.halted:
+            print ("halted - not executing", name)
+            return
+
         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
         asmop = yield from self.get_assembly_name()
@@ -538,6 +543,10 @@ class ISACaller:
             self.pc.update(self.namespace)
             return
 
+        if name == 'attn':
+            self.halted = True
+            return
+
         info = self.instrs[name]
         yield from self.prep_namespace(info.form, info.op_fields)