From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 15 May 2020 20:48:43 +0000 (+0100)
Subject: add reg allocation requirements
X-Git-Tag: div_pipeline~1160
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3197efe5bc678d2ea44b2b5b62cd29c8798f8abc;p=soc.git

add reg allocation requirements
---

diff --git a/libreriscv b/libreriscv
index 2d8ae9db..f7602e59 160000
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 2d8ae9db6019c3a7ed881f14612f2b66bb263a9e
+Subproject commit f7602e599e6557e45249b80d888631a9cf241cb7
diff --git a/src/soc/branch/pipe_data.py b/src/soc/branch/pipe_data.py
index 710e5e1e..f3bb8f13 100644
--- a/src/soc/branch/pipe_data.py
+++ b/src/soc/branch/pipe_data.py
@@ -15,6 +15,22 @@ class IntegerData:
     def eq(self, i):
         return [self.ctx.eq(i.ctx)]
 
+"""
+    def op_b(LR):
+    def op_ba(LR):
+    def op_bl(LR):
+    def op_bla(LR):
+    def op_bc(LR, CR, CTR):
+    def op_bca(LR, CR, CTR):
+    def op_bcl(LR, CR, CTR):
+    def op_bcla(LR, CR, CTR):
+    def op_bclr(LR, CR, CTR):
+    def op_bclrl(LR, CR, CTR):
+    def op_bcctr(LR, CR, CTR):
+    def op_bcctrl(LR, CR, CTR):
+    def op_bctar(LR, CR, CTR, TAR):
+    def op_bctarl(LR, CR, CTR, TAR):
+"""
 
 class BranchInputData(IntegerData):
     def __init__(self, pspec):