From: Daniel Benusovich <flyingmonkeys1996@gmail.com>
Date: Sun, 21 Apr 2019 20:45:41 +0000 (-0700)
Subject: Add external access to table size to plru
X-Git-Tag: div_pipeline~2203
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3198081936cde0efa0934a3948b9f14023cf436a;p=soc.git

Add external access to table size to plru
---

diff --git a/TLB/src/ariane/plru.py b/TLB/src/ariane/plru.py
index c8b26031..50951c1f 100644
--- a/TLB/src/ariane/plru.py
+++ b/TLB/src/ariane/plru.py
@@ -22,8 +22,8 @@ class PLRU:
         self.replace_en_o = Signal(entries)
         self.lu_access_i = Signal()
         # Tree (bit per entry)
-        TLBSZ = 2*(self.entries-1)
-        self.plru_tree = Signal(TLBSZ)
+        self.TLBSZ = 2*(self.entries-1)
+        self.plru_tree = Signal(self.TLBSZ)
 
     def elaborate(self, platform):
         m = Module()