From: Anton Blanchard <anton@linux.ibm.com>
Date: Mon, 9 Sep 2019 06:00:49 +0000 (+1000)
Subject: More second write port removal
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=31a6fb6ef54a33038ea63a469f13a2d28feacc9e;p=microwatt.git

More second write port removal

I missed the register file updates for the second write port
removal.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
---

diff --git a/common.vhdl b/common.vhdl
index 29c37be..c12f8b1 100644
--- a/common.vhdl
+++ b/common.vhdl
@@ -170,11 +170,8 @@ package common is
 		write_reg : std_ulogic_vector(4 downto 0);
 		write_data : std_ulogic_vector(63 downto 0);
 		write_enable : std_ulogic;
-		write_reg2 : std_ulogic_vector(4 downto 0);
-		write_data2 : std_ulogic_vector(63 downto 0);
-		write_enable2 : std_ulogic;
 	end record;
-	constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_enable2 => '0', others => (others => '0'));
+	constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', others => (others => '0'));
 
 	type WritebackToCrFileType is record
 		write_cr_enable : std_ulogic;
diff --git a/register_file.vhdl b/register_file.vhdl
index 7a6b513..9995374 100644
--- a/register_file.vhdl
+++ b/register_file.vhdl
@@ -31,11 +31,6 @@ begin
 				report "Writing GPR " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data);
 				registers(to_integer(unsigned(w_in.write_reg))) <= w_in.write_data;
 			end if;
-			if w_in.write_enable2 = '1' then
-				assert not(is_x(w_in.write_data2)) and not(is_x(w_in.write_reg2)) severity failure;
-				report "Writing GPR " & to_hstring(w_in.write_reg2) & " " & to_hstring(w_in.write_data2);
-				registers(to_integer(unsigned(w_in.write_reg2))) <= w_in.write_data2;
-			end if;
 		end if;
 	end process register_write_0;