From: Kevin Lim Date: Fri, 14 Jul 2006 21:54:43 +0000 (-0400) Subject: Merge ktlim@zizzer:/bk/newmem X-Git-Tag: m5_2.0_beta1~64^2~11 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=31ac8e733765ee37411d92ea3b7c308affef087a;p=gem5.git Merge ktlim@zizzer:/bk/newmem into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge configs/test/fs.py: configs/test/test.py: SCCS merged --HG-- extra : convert_revision : 7b2dbcd5881fac01dec38001c4131e73b5be52b5 --- 31ac8e733765ee37411d92ea3b7c308affef087a diff --cc configs/test/fs.py index 55fed7234,41c3f8cc0..f4c50fc23 --- a/configs/test/fs.py +++ b/configs/test/fs.py @@@ -22,16 -17,118 +22,18 @@@ if args # Base for tests is directory containing this file. test_base = os.path.dirname(__file__) + script.dir = '/z/saidi/work/m5.newmem/configs/boot' + linux_image = env.get('LINUX_IMAGE', disk('linux-latest.img')) -class IdeControllerPciData(PciConfigData): - VendorID = 0x8086 - DeviceID = 0x7111 - Command = 0x0 - Status = 0x280 - Revision = 0x0 - ClassCode = 0x01 - SubClassCode = 0x01 - ProgIF = 0x85 - BAR0 = 0x00000001 - BAR1 = 0x00000001 - BAR2 = 0x00000001 - BAR3 = 0x00000001 - BAR4 = 0x00000001 - BAR5 = 0x00000001 - InterruptLine = 0x1f - InterruptPin = 0x01 - BAR0Size = '8B' - BAR1Size = '4B' - BAR2Size = '8B' - BAR3Size = '4B' - BAR4Size = '16B' - -class SinicPciData(PciConfigData): - VendorID = 0x1291 - DeviceID = 0x1293 - Status = 0x0290 - SubClassCode = 0x00 - ClassCode = 0x02 - ProgIF = 0x00 - BAR0 = 0x00000000 - BAR1 = 0x00000000 - BAR2 = 0x00000000 - BAR3 = 0x00000000 - BAR4 = 0x00000000 - BAR5 = 0x00000000 - MaximumLatency = 0x34 - MinimumGrant = 0xb0 - InterruptLine = 0x1e - InterruptPin = 0x01 - BAR0Size = '64kB' - -class NSGigEPciData(PciConfigData): - VendorID = 0x100B - DeviceID = 0x0022 - Status = 0x0290 - SubClassCode = 0x00 - ClassCode = 0x02 - ProgIF = 0x00 - BAR0 = 0x00000001 - BAR1 = 0x00000000 - BAR2 = 0x00000000 - BAR3 = 0x00000000 - BAR4 = 0x00000000 - BAR5 = 0x00000000 - MaximumLatency = 0x34 - MinimumGrant = 0xb0 - InterruptLine = 0x1e - InterruptPin = 0x01 - BAR0Size = '256B' - BAR1Size = '4kB' - -class LinuxRootDisk(IdeDisk): - raw_image = RawDiskImage(image_file=linux_image, read_only=True) - image = CowDiskImage(child=Parent.raw_image, read_only=False) - -class LinuxSwapDisk(IdeDisk): - raw_image = RawDiskImage(image_file = disk('linux-bigswap2.img'), - read_only=True) - image = CowDiskImage(child = Parent.raw_image, read_only=False) - -class SpecwebFilesetDisk(IdeDisk): - raw_image = RawDiskImage(image_file = disk('specweb-fileset.img'), - read_only=True) - image = CowDiskImage(child = Parent.raw_image, read_only=False) +class CowIdeDisk(IdeDisk): + image = CowDiskImage(child=RawDiskImage(read_only=True), + read_only=False) + + def childImage(self, ci): + self.image.child.image_file = ci class BaseTsunami(Tsunami): - cchip = TsunamiCChip(pio_addr=0x801a0000000) - pchip = TsunamiPChip(pio_addr=0x80180000000) - pciconfig = PciConfigAll() - fake_sm_chip = IsaFake(pio_addr=0x801fc000370) - - fake_uart1 = IsaFake(pio_addr=0x801fc0002f8) - fake_uart2 = IsaFake(pio_addr=0x801fc0003e8) - fake_uart3 = IsaFake(pio_addr=0x801fc0002e8) - fake_uart4 = IsaFake(pio_addr=0x801fc0003f0) - - fake_ppc = IsaFake(pio_addr=0x801fc0003bc) - - fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000) - - fake_pnp_addr = IsaFake(pio_addr=0x801fc000279) - fake_pnp_write = IsaFake(pio_addr=0x801fc000a79) - fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203) - fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243) - fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283) - fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3) - fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303) - fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343) - fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383) - fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3) - - fake_ata0 = IsaFake(pio_addr=0x801fc0001f0) - fake_ata1 = IsaFake(pio_addr=0x801fc000170) - - fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer') - io = TsunamiIO(pio_addr=0x801fc000000) - uart = Uart8250(pio_addr=0x801fc0003f8) ethernet = NSGigE(configdata=NSGigEPciData(), pci_bus=0, pci_dev=1, pci_func=0) etherint = NSGigEInt(device=Parent.ethernet) @@@ -39,39 -143,61 +41,41 @@@ pci_func=0, pci_dev=0, pci_bus=0) class MyLinuxAlphaSystem(LinuxAlphaSystem): - magicbus = Bus(bus_id=0) - magicbus2 = Bus(bus_id=1) + iobus = Bus(bus_id=0) + membus = Bus(bus_id=1) bridge = Bridge() physmem = PhysicalMemory(range = AddrRange('128MB')) - bridge.side_a = magicbus.port - bridge.side_b = magicbus2.port - physmem.port = magicbus2.port - tsunami = LinuxTsunami() - tsunami.cchip.pio = magicbus.port - tsunami.pchip.pio = magicbus.port - tsunami.pciconfig.pio = magicbus.default - tsunami.fake_sm_chip.pio = magicbus.port - tsunami.ethernet.pio = magicbus.port - tsunami.ethernet.dma = magicbus.port - tsunami.ethernet.config = magicbus.port - tsunami.fake_uart1.pio = magicbus.port - tsunami.fake_uart2.pio = magicbus.port - tsunami.fake_uart3.pio = magicbus.port - tsunami.fake_uart4.pio = magicbus.port - tsunami.ide.pio = magicbus.port - tsunami.ide.dma = magicbus.port - tsunami.ide.config = magicbus.port - tsunami.fake_ppc.pio = magicbus.port - tsunami.fake_OROM.pio = magicbus.port - tsunami.fake_pnp_addr.pio = magicbus.port - tsunami.fake_pnp_write.pio = magicbus.port - tsunami.fake_pnp_read0.pio = magicbus.port - tsunami.fake_pnp_read1.pio = magicbus.port - tsunami.fake_pnp_read2.pio = magicbus.port - tsunami.fake_pnp_read3.pio = magicbus.port - tsunami.fake_pnp_read4.pio = magicbus.port - tsunami.fake_pnp_read5.pio = magicbus.port - tsunami.fake_pnp_read6.pio = magicbus.port - tsunami.fake_pnp_read7.pio = magicbus.port - tsunami.fake_ata0.pio = magicbus.port - tsunami.fake_ata1.pio = magicbus.port - tsunami.fb.pio = magicbus.port - tsunami.io.pio = magicbus.port - tsunami.uart.pio = magicbus.port - tsunami.console.pio = magicbus.port - raw_image = RawDiskImage(image_file=disk('linux-latest.img'), - read_only=True) - simple_disk = SimpleDisk(disk=Parent.raw_image) + bridge.side_a = iobus.port + bridge.side_b = membus.port + physmem.port = membus.port + disk0 = CowIdeDisk(driveID='master') + disk2 = CowIdeDisk(driveID='master') + disk0.childImage(linux_image) + disk2.childImage(disk('linux-bigswap2.img')) + tsunami = BaseTsunami() + tsunami.attachIO(iobus) + tsunami.ide.pio = iobus.port + tsunami.ide.dma = iobus.port + tsunami.ide.config = iobus.port + tsunami.ethernet.pio = iobus.port + tsunami.ethernet.dma = iobus.port + tsunami.ethernet.config = iobus.port + simple_disk = SimpleDisk(disk=RawDiskImage(image_file = linux_image, + read_only = True)) intrctrl = IntrControl() - if options.timing: + if options.detailed: + cpu = DetailedO3CPU() + elif options.timing: cpu = TimingSimpleCPU() + mem_mode = 'timing' else: cpu = AtomicSimpleCPU() - cpu.mem = magicbus2 - cpu.icache_port = magicbus2.port - cpu.dcache_port = magicbus2.port + cpu.mem = membus + cpu.icache_port = membus.port + cpu.dcache_port = membus.port cpu.itb = AlphaITB() cpu.dtb = AlphaDTB() + cpu.clock = '2GHz' sim_console = SimConsole(listener=ConsoleListener(port=3456)) kernel = binary('vmlinux') pal = binary('ts_osfpal') @@@ -90,21 -220,23 +94,29 @@@ def DualRoot(clientSystem, serverSystem self.etherlink = EtherLink(int1 = Parent.client.tsunami.etherint[0], int2 = Parent.server.tsunami.etherint[0], dump = Parent.etherdump) - self.clock = '5GHz' + self.clock = '1THz' return self -root = DualRoot( - MyLinuxAlphaSystem(readfile=script('netperf-stream-nt-client.rcS')), - MyLinuxAlphaSystem(readfile=script('netperf-server.rcS'))) +if options.dual: + root = DualRoot( + MyLinuxAlphaSystem(readfile=script('netperf-stream-nt-client.rcS')), + MyLinuxAlphaSystem(readfile=script('netperf-server.rcS'))) +else: + root = TsunamiRoot(clock = '2GHz', system = MyLinuxAlphaSystem()) m5.instantiate(root) + #exit_event = m5.simulate(2600000000000) + #if exit_event.getCause() != "user interrupt received": + # m5.checkpoint(root, 'cpt') + # exit_event = m5.simulate(300000000000) + # if exit_event.getCause() != "user interrupt received": + # m5.checkpoint(root, 'cptA') + + -exit_event = m5.simulate() +if options.maxtick: + exit_event = m5.simulate(options.maxtick) +else: + exit_event = m5.simulate() print 'Exiting @ cycle', m5.curTick(), 'because', exit_event.getCause() diff --cc configs/test/test.py index 79b271c3f,feb44e2d1..e1b75f4bc --- a/configs/test/test.py +++ b/configs/test/test.py @@@ -36,8 -70,23 +36,13 @@@ if options.detailed process += [smt_process, ] smt_idx += 1 - cpu = DetailedO3CPU() -else: - cpu = AtomicSimpleCPU() cpu.workload = process -cpu.mem = magicbus -cpu.icache_port=magicbus.port -cpu.dcache_port=magicbus.port - -system = System(physmem = mem, cpu = cpu) + if options.timing or options.detailed: + system.mem_mode = 'timing' + + -mem.port = magicbus.port -root = Root(system = system) + # instantiate configuration m5.instantiate(root) diff --cc src/cpu/simple/atomic.cc index 0580fdd81,1752b2b5b..6be188a96 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@@ -168,21 -168,18 +169,28 @@@ AtomicSimpleCPU::serialize(ostream &os void AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) { - UNSERIALIZE_ENUM(_status); - BaseSimpleCPU::unserialize(cp, section); + SimObject::State so_state; + UNSERIALIZE_ENUM(so_state); tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); + BaseSimpleCPU::unserialize(cp, section); +} + +void +AtomicSimpleCPU::resume() +{ + if (thread->status() == ThreadContext::Active) { + if (!tickEvent.scheduled()) + tickEvent.schedule(curTick); + } } + void + AtomicSimpleCPU::resume() + { + assert(system->getMemoryMode() == System::Atomic); + changeState(SimObject::Running); + } + void AtomicSimpleCPU::switchOut() { diff --cc src/cpu/simple/atomic.hh index b602af558,d59ca01aa..895eb5bde --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@@ -126,8 -126,8 +126,9 @@@ class AtomicSimpleCPU : public BaseSimp virtual void serialize(std::ostream &os); virtual void unserialize(Checkpoint *cp, const std::string §ion); + virtual void resume(); + virtual void resume(); void switchOut(); void takeOverFrom(BaseCPU *oldCPU);