From: Sebastien Bourdeauducq Date: Thu, 29 Nov 2012 22:47:08 +0000 (+0100) Subject: corelogic/roundrobin: fix request width X-Git-Tag: 24jan2021_ls180~2099^2~732 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=31c722f993f47b97a9e66a893045d2e765722d16;p=litex.git corelogic/roundrobin: fix request width --- diff --git a/migen/corelogic/roundrobin.py b/migen/corelogic/roundrobin.py index 4b754655..298c7d16 100644 --- a/migen/corelogic/roundrobin.py +++ b/migen/corelogic/roundrobin.py @@ -5,7 +5,7 @@ from migen.fhdl.structure import * class RoundRobin: def __init__(self, n, switch_policy=SP_WITHDRAW): self.n = n - self.request = Signal(max=self.n) + self.request = Signal(nbits=self.n) self.grant = Signal(max=self.n) self.switch_policy = switch_policy if self.switch_policy == SP_CE: